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Monday 4/6

 

This name stands for the combination of an energy-efficient Arm?-Core and the high-speed peripherals of the QorIQ? Power? architecture. The Arm? CPU core is connected to the communication unit via a new bus system "Cache Coherent Interconnect" (CCI400).

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Short overview Layerscape series
 

As SEGGER strengthens its position within the RISC-V instruction set architecture, the company announced its J-Link probes deliver support for the new SiFive Insight debug/trace solution.
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Barcelona Supercomputing Center (BSC) began a new project called AMPERE. It is a model-driven development framework for parallel and energy-efficient computation supporting multi-criteria optimization.
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Pixelworks and TCL Communication announced the companies have extended its collaboration to further advance the display capabilities and performance of its smartphone lineup. The TCL 10 Pro, 10L, and 10 5G are the first phones developed under the partnership.
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In part 1 of this series, we covered the importance of security in connected embedded systems and the dis-integration of Flash forcing the use of external Flash. In part 2 of this series, we will cover Secure Flash, the next generation of smart memory.

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Secure Processing Environment
 

 
 
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