IOxOS Technologies Drives Scalable Architecture for Radar Frontends
August 20, 2026
News
IOxOS Technologies sees the combination of FPGA Mezzanine Card (FMC) modules, built on the open VITA 57.1 standard, with high-end FPGA carrier boards, for a resolute architectural methodology to the design of scalable radar frontends.
FMC VITA 57.1 Standard Benefits:
- Enable interoperability across vendors with standardized mechanical and electrical interface between FMC modules and carrier boards, reducing integration risk
- High Pin Count (HPC) and Low Pin Count (LPC) connector variants
- Standardized high-speed serial lanes suited to ADC/DAC and RF front-end interfaces generally necessary in radar acquisition
According to the release, the FPGA processing capability may be decoupled from the analog and digital front-end interfaces, provided by interchangeable FMC modules. A given carrier platform can be reconfigured to support new sensor interfaces without redesigning the entire compute architecture.
IOxOS Technologies offers solutions via its partnerships with DONALBA in Spain and powerBridge Computer Vertriebs GmbH in Germany.
For more information, visit www.ioxos.ch.
Chad Cox is the Production Editor at Embedded Computing Design. His responsibilities are centered around content creation, writing and editing, and article research and development. Chad covers industry news and events and is known to interact with various industrial leaders via on-premise visits and online interviews. He is responsible for the digital footprint and dissemination of news via social media posts, advertising creation and the production of newsletters including the Embedded Computing Design’s Daily.
He is well versed in many facets of industrial computing including Edge AI, IoT, Processing, Security, Open Source, and more.
Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature and holds a master’s in education.
