FPGAs offer a wide range of cost/performance for implementing DSP algorithms. Finding the optimal implementation usually involves exploring the tradeoffs between fully parallel vs. serial architectures of the algorithm and will be highly dependent on the available resources, speed, and architecture of the FPGA device. This e-cast will explore how these optimizations work and how they can be applied automatically to high-level algorithm models using Synplicity's Synplify DSP tool. The seminar will include examples in wireless communications and will benefit HW and system engineers who are interested in: - Methods to rapidly describe algorithms and explore speed/area optimization tradeoffs - Creating algorithms and IP that are easily portable and optimized across vastly different FPGA technologies