Senior verification technical lead


? Expertise in developing testbench in block level as well as SOC level. ? Experienced in verification using UVM, OVM, VMM methodologies. ? Developed UVM/OVM/SystemVerilog based verification environment. ? Developed Verification plan, environment architecture documents, test plan. ? Developed verification environment components including monitor, driver, scoreboard, environment. ? Developed reference model in UVM for tributary time slots block for OTN .

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Debug & Test

Performing End-to-End Traffic Traceability Using Functional Coverage - Story

April 01, 2020

For each of the functional features of a DUT to verify, all possible stimulus generation is developed through test cases and with the help of scoreboard, models, checkers, and assertions.

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