Delivering security at speed in Compute Express Link™ (CXL) is critical to solving the bandwidth bottleneck in data center infrastructure. Integrity and Data Encryption (IDE) monitors and protects against physical attacks on CXL and PCI Express® (PCIe) links. CXL requires extremely low latency to enable load-store memory architectures and cache-coherent links for its targeted use cases.

Rambus Inc. announced the Rambus HBM3-ready memory interface subsystem consisting of a fully-integrated PHY (1) and digital controller (2). Supporting data rates of up to 8.4 Gbps, the solution is designed to deliver over a terabyte per second of bandwidth, more than double that of high-end HBM2E memory subsystems.

The PCI Express (PCIe) specification had remained at the 3.0 generation for almost seven years (from 2010-2017), with lanes running at 8 Gigatransfers per second (GT/s).

The CryptoManager Root of Trust RT-640 and RT-645 are available for licensing. In addition to a robust Root of Trust framework with functional safety at ASIL-B and -D levels.

Rambus announced the release of its 800G MACsec (Media Access Control security) for networking infrastructures.

Rambus, a silicon IP and chip provider, announced it now offers a comprehensive and optimized interface solution designed for PCI Express (PCIe) 5.0, with backward compatibility to PCIe.