Rambus introduced its Rambus PCIe 7.0 Switch IP with Time Division Multiplexing (TDM) engineered to meet industrial challenges such as escalating bandwidth, latency, and scalability requirements of AI, cloud, and high-performance computing (HPC) systems.

Rambus introduced a SOCAMM2 (Small Outline Compression Attached Memory Module) chipset engineered for low-power, high-performance LPDDR5X-based memory modules for AI servers. The new SKUs enhance Rambus’s offering of complete memory interface chipsets for all JEDEC-standard DDR5 and LPDDR5 memory modules.

Systems are demanding more from their memory subsystems, and they can get it thanks to the latest controller from Rambus, as evidenced in the discussion between Rambus' Bart Stevens and Embedded Computing Design's Rich Nass.

Rambus Inc. announced its HBM4E Memory Controller IP capable of facilitating innovative HBM memory deployments for next-generation AI accelerators, graphics, and HPC applications. It operates at up to 16 Gigabits per second (Gbps) per pin delivering a throughput of 4.1 Terabytes per second (TB/s) to each memory device. For an AI accelerator with eight attached HBM4E devices, this translates to over 32 TB/s of memory bandwidth for demanding AI workloads.

Rambus Inc., a chip and silicon IP provider, has announced the availability of complete client chipsets for next-generation AI PC memory modules, featuring two new Power Management ICs (PMICs) for client computing.

Rambus Inc. announced the introduction of its next-generation CryptoManager Security IP solutions, including Root of Trust, Hub, and Core families. The CryptoManager Security IP offerings are designed to deliver functional integration and security, enabling customers to choose the level of security features and capabilities for their applications.

SAN JOSE, Calif.--Rambus Inc. unveiled industry-first, complete memory interface chipsets for Gen5 DDR5 RDIMMs and next-generation DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMMs).