Embedded Computing Design

This five-part series presents an electromagnetic (EM) field-oriented perspective on PCB design intended to help engineers pass electromagnetic interference (EMI) compliance testing. The same techniques used to reduce EMI also mitigate interference, suggesting a universal PCB layout philosophy. Parts 1 and 2 established the foundational physics and illustrated through practical examples how decisions such as signal layer transitions, shared ground planes, and imperfect transmission lines become sources of radiation. Parts 3 and 4 extended those principles into a practical layout workflow: schematic-to-placement strategy, grounding architecture, power system routing, and stack-up selection. This final article addresses the specialized layout requirements that arise in the most demanding designs. Every design, regardless of signal type, must manage heat—not only to protect components but also to prevent thermoelectrically generated offsets from corrupting sensitive measurements. Together, these considerations complete the picture of what it takes to plan and execute a board layout that passes EMI compliance the first time.

With schematic review, parts placement, and grounding architecture addressed in Part 3, this article turns to the routing decisions that follow. Power system routing deserves attention early in the layout process—before the signal routing begins—because it is one of the largest consumers of board area and directly influences the layer count and stack-up selection. Part 4 of this article series presents a systematic procedure for determining the correct number of layers and the optimal stack-up configuration, from 2-layer through 8-layer designs, ensuring that every signal has a dedicated, field-contained transmission path. Following this procedure from the start of layout eliminates the costly need to restart a design partway through.

The first two parts of this series established the fundamental physics of field confinement on a PCB and presented practical layout techniques for minimizing electromagnetic interference (EMI), interference, and susceptibility to external fields. Part 3 of this series addresses the critical early decisions that determine the success of any complex board layout: how to translate schematic intent into a sound placement strategy, and how to choose the right grounding architecture before routing begins. It examines how to organize the schematic for layout readiness, how to use differential signaling to preserve ground fidelity, and when to select a ground tree over a solid ground plane. Getting these foundational decisions right from the start is the surest path to a board that passes EMI compliance the first time.

Any product designed today that requires high speed clocks can be troubled with electromagnetic compatibility (EMC) compliance issues. This article outlines an electromagnetic (EM) field-oriented perspective for printed circuit board (PCB) design intended to help the reader pass electromagnetic interference (EMI) testing the first time. The same techniques used for reducing EMI will mitigate interference, suggesting a universal PCB layout philosophy. This second article covers several PCB interconnect examples illustrating exactly how to implement the techniques presented in Part 1. Finally, Part 3 will discuss PCB layout strategies for complex boards that will satisfy the presented solutions.

Any product designed today that requires high-speed clocks can be troubled with electromagnetic compatibility (EMC) compliance issues. This article outlines an electromagnetic (EM) field-oriented perspective for printed circuit board (PCB) design intended to help the reader pass electromagnetic interference (EMI) compliance testing the first time