Architecture exploration has been the holy grail of product design. It has the potential to completely transform product engineering. Research and use cases evaluations have shown that 80% of system optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration.
In Part 1 of this two-part series we addressed the need for early-stage power analysis in complex SoCs and system designs, and introduced the VisualSim graphical modeling tool as a comprehensive energy simulation solution. In Part 2, we show how VisualSim performs when forecasting and expressing power values across several scenarios (offset concurrent tasks; comparing a single core at 1 GHz to four cores at 250 MHz; dynamic voltage frequency scaling (DVFS); and power gating) in a multicore embedded environment.
With the increase in SoC design complexity, system-level power estimation is becoming a critical factor. Part one of this two-part series explains why this is the case and introduces a comprehensive modeling platform for evaluating the power consumption of subsystems, chips, and entire systems.
The pandemic sweeping the world, COVID-19, has rendered a large proportion of the workforce unable to commute to work, as to mitigate the spread of the virus.
For any new system, the number of power states, concurrent thread operations, transition times and switching require a detailed power evaluation prior to finalizing the specification.
Power management is a critical design factor in electronics. Product features of consumer application, space-based systems, data center solutions, high-performance computing are constrained by budget.