10X Faster Concurrent Full-Chip Optimization and Signoff from Cadence

By Chad Cox

Associate Editor

Embedded Computing Design

October 18, 2022

News

10X Faster Concurrent Full-Chip Optimization and Signoff from Cadence
Image Provided by Cadence Design Systems

SAN JOSE, Calif. Cadence Design Systems, Inc. released its Cadence Certus Closure Solution for the automation and acceleration of a full design closure cycle (from signoff optimization through routing, static timing analysis (STA) and extraction) overnight. Benefits of the solution include: Innovative scalable architecture, Incremental signoff, Improved engineering productivity, SmartHub interface, 3D-IC design efficiencies.

The platform allows for large chip design with infinite size and enhancing productivity by 10X when compared to modern solutions. Dr., senior vice president and general manager in the Digital & Signoff Group at Cadence explains, “Today’s design teams often spend five to seven days per iteration to meet chip-level signoff timing and power requirements, and previous methodologies failed to deliver the team collaboration and user experience needed for efficient design closure.”

Dr. Chin-Chi Teng continues,  “We are intensely in tune with the needs of the design community, and with the release of the new Cadence Certus Closure Solution, we’re offering our customers a novel environment for chip-level optimization and signoff that delivers exceptional PPA results within a matter of hours. With this new Cadence solution, we’re empowering customers to achieve productivity goals and deliver products to market faster.”

The Cadence Certus Closure Solution generates a complete automated ecosystem enabling full-chip optimization through Cadence’s Innovus Implementation System and the Tempus Timing Signoff Solution disposing of repetitive loops with block proprietors and the ability for designers to make instant decisions when concerned with optimization and choices with signoff.

With the Cadence Certus Closure Solution, Hyperscale computing, 5G communications, mobile, automotive, and networking design has improved for signoff closure constrictions making development simpler by design.

For more information, visit www.cadence.com/go/certuspr.

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