Renesas Pioneers RISC-V Technology With RZ/Five General-Purpose MPUs Based on 64-Bit RISC-V CPU Core - NewsMarch 03, 2022
Renesas Electronics Corporation's RZ/Five employs the Andes AX45MP, based on the RISC-V CPU instruction set architecture (ISA). The RZ/Five augments Renesas’ previously available Arm® CPU core-based MPUs, expanding customer options and providing more flexibility in the product development process.
Champions of the open-standard ISA expect it to start displacing competitive offerings en masse over the next few years. While that remains to be seen, the introduction of custom RISC-V instruction extensions, the formation industry-specific working groups, and advances in tools are redefining the technology’s true winners.
San Francisco-based fabless semiconductor company SiFive has launched its second high-performance processor P650 claiming to be the fastest licensable RISC-V processor IP core in the market. Within 6 months of the initial launch of the P550, the manufacturer realized the need for some significant upgrades in terms of the performance directly linking to the clock speed frequency.
RISC-V members ratified the Vector, Scalar Cryptography, and Hypervisor specifications, which will help unlock new opportunities for developers creating RISC-V applications for artificial intelligence (AI) and machine learning (ML), the Internet of Things (IoT), connected and autonomous cars, data centers, and beyond.
STEM fields have long struggled with a lack of diversity. A recent report from Lindström Group highlighted the problem in a microcosm, revealing that just 12% of engineers and 16% of engineering students in the United Kingdom are women.
There’s no moss gathering on the RISC-V stone. The group continues to make progress in just about all facets of its roadmap.
RISC-V International and CHIPS Alliance announced a collaboration to update the OmniXtend Cache Coherency specification and protocol, along with building out developer tools for OmniXtend.