Hello Embedded Engineers and Developers! Welcome to In Case You Missed it: Embedded Insights, the weekly news show all about Embedded technologies and solutions from Embedded Computing Design.

During October 22–23, 2025, RISC-V International will host the RISC-V Summit North America 2025 at the Santa Clara Convention Center where industry leaders, researchers, and designers will come together to advance the open standard ISA.  

In this episode of Embedded Insiders, we’re joined by RISC-V’s newest CEO, Andrea Gallo, who outlines his vision for the company’s future. From accelerating ecosystem growth to his expectations for current architectures, Gallo shares his strategy to shape the next chapter of RISC-V.

RISC-V International has announced Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since June 2024, where he's helped to facilitate the technical vision of RISC-V International, working closely with RISC-V members around the globe to drive further adoption of the RISC-V Instruction Set Architecture (ISA). RISC-V International will soon hire a replacement for the Vice President of Technology role.

Santa Clara, California. RISC-V International revealed the ratification of the RVA23 Profile. RVA Profiles allow implementations of RISC-V 64-bit application processors that run OS stacks from standard binary OS distributions.

On this episode of Embedded Insiders, we’re joined by Calista Redmond, CEO of RISC-V International, and Andrea Gallo, VP of Technology, as they dive into the organization’s latest technical breakthroughs, the evolving RISC-V software ecosystem, and how RISC-V is making an impact in the AI/ML sectors—and beyond.

Microchip is packing up in Chandler, Arizona and will start its trip to the RISC-V Summit in Santa Clara, California, November 7^th and 8^th, 2023, and November 6 being Member Day. Microchip will be demonstrating its market leading FPGA solutions for the intelligent edge and how it leverages the RISC-V ISA to design heterogenous processing architectures for non-proprietary instruction set architectures.