Agile Analog recently made available a full set of analog IP designed to accelerate IoT designs. The blocks envelop a device’s processor core and memory to provide the analog functions needed to facilitate communications between the digital and the analog aspects of IoT devices.

Agile Analog released a full set of the key analog IPs set in six blocks around the client’s processor and memory hardware for critical analog tasks needed for an interface between the digital and analog realm. "Effectively this provides a foundation toolkit for all the analog parts that a design might possibly need to fast track, simplify and re-risk the design process," says Barry Paterson, Agile Analog's CEO, "We have included all the features and functions that a customer would require so that they can select exactly what they require from the set without worrying that they missed something vital.

New DSCL allows for the implementation of the digital circuits needed to manage analog blocks in mixed signal solutions.

Agile Analog has made its new RC Oscillator IP available for purchase. This is the first in a new family of analog IP blocks that the company is introducing to make it easier to integrate analog circuits onto ASICs.

Agile Analog has signed its first licensee in China. “We opened our APAC regional sales and engineering office in January this year,” said Barry Paterson, Agile Analog’s CEO. “We thought that there would be a big demand for our unique analog IP solutions in the Asia-Pacific region and so we are delighted to have signed our first license for the region in just a couple of months. Key to the deal is us having local support for the customer to provide immediate answers to any engineering questions.”

The current fab capacity challenges within the semiconductor industry have resulted in ASIC and fabless companies evaluating multiple foundries in order to meet chip production forecasts for the next several quarters. Agile Analog’s process-agnostic Composa™ technology addresses the problem of portability of the analog IP cores that have traditionally required re-engineering to suit each different silicon process technology.