Agile Analog’s IP Block Set Helps Accelerate IoT Design Process
November 07, 2022
News
Agile Analog recently made available a full set of analog IP designed to accelerate IoT designs. The blocks envelop a device’s processor core and memory to provide the analog functions needed to facilitate communications between the digital and the analog aspects of IoT devices.
The analog IP is composed of six blocks that, according to Agile Analog’s CEO Barry Paterson, can be customized and used on an as-needed basis according to the requirements of unique designs.
The set’s six blocks include:
- SoC/ASIC Security Protection block with voltage glitch and temperature sensors
- Sensor Interface block with 8/10-bit SAR ADC, 8/10-bit DAC, and a low-power programmable comparator
- Always-on block with a low-power RC oscillator, low-power bandgap, compact digital standard cell library, low-power programmable comparator, and power on rest
- IC Health and Monitoring block with temperature and IR drop sensors
- Power block with low dropout regulator, power on reset, IR drop sensor, and low power bandgap
- Radio Interface block with 8/10-bit SAR ADC, 8/10-bit DAC, RC oscillator, and low dropout regulator
The configurable nature of the analog IP blocks allows for customization of the components within to ensure each block best suits the IoT device’s overall needs. For instance, the power block could house multiple agileLDOs that would supply the necessary internal voltage rails alongside an agilePOR that would guarantee the SoC starts only in the presence of stable voltage rails.
To address key concerns about SoC security, that block uses voltage and temperature sensors to monitor attack vectors that would manipulate those measurements with the company’s agileVGlitch and agileTsense.
Additionally, the IC Heath and Monitoring block utilizes agileTsense technology to monitor the SoC die temperature, while the agileIR DROP monitors long-term aging effects. The Radio Interface block provides support for any radio interface a design may require, such as LoRa or low-power Bluetooth.
Agile Analog fully supports the IP block set for the design phase to ensure that it meets the power, performance, and area requirements of the design, including supporting the integration of the IP into the overall design. This is made easier not only by the internal connection of the IP within the blocks, but also their external interfaces, which allow them to look like digital blocks and be dropped into the digital design flow.
These blocks are generated and validated for customers’ specific process and node requirements by Agile Analog’s Composa™ technology, which can also assist in rapid solution regeneration should those requirements change; this flexibility contributes to easing portability between foundries and processes. All the major foundries are supported including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.
For more information, visit Agile Analog.
