Point2 P1B121 SoC is Transforming AI/ML Datacenters with Ultra-Low Latency and Energy Efficiency
November 19, 2024
News
San Jose, California. Point2 Technology introduced the Point2 P1B12,1 its innovative Smart Retimer system-on-chip (SoC) for AEC applications in hyperscale AI/ML datacenters. It incorporates eight-unidirectional SerDes channels with smart Clock Data Recovery (CDR)/Retimer operations that support 112G PAM4 and 56G NRZ data rates. The Point2 P1B121 is designed for low-power and low-latency operations in 800 gigabit (800G) and 1.6 Terabit (1.6T) Active Electrical Cables (AECs). At 3 nanoseconds (3ns), the P1B121 chip latency is 20X lower than standard DSP-based PAM4 Retimers.
Point2’s SoCs include Bit Error Rate (BER) architecture resulting in what the company calls the industry’s most energy-efficient interconnect SoC delivering AECs with 2X lower power consumption than other solutions on the market. The technology enables the manufacturing of AECs utilizing smaller copper wire gauges, reducing cable volume and extending cable length when compared to general copper cabling.
“At Point2, we continue to push the limits on power efficiency and sustainability inside the datacenter. We recognize the challenges datacenters face in balancing high-performance and low-latency operations with the need for energy efficiency,” said Sean Park, founder, and CEO of Point2 Technology. “The Point2 P1B121 Smart Retimer SoC is a key solution in addressing those challenges directly and giving datacenters the ability to not only address current 800G data interconnect speeds but prepare for future 1.6T workloads as well.”
Highlights:
- Designed for 800G/1600G AECs
- Adaptable line equalization to optimize power, performance, and cable length
- Bounded Gearbox transposes 2x56G between 1x112G. Reduces copper twin-ax count by 50% for 400G AECs
- Power consumption at 3.0W per chip, or 6.5W in an 800G paddle card
- Latency at 3ns
- Intelligent Diagnostics for reliability, availability, and serviceability of network
- Serializer (TX) with programmable FIR filter and pre-emphasis
- De-serializer (RX) with programmable continuous time linear equalizer (CTLE) and decision-feedback equalizer (DFE) to mitigate Rx channel loss
- Low sensitivity and adjustable data sampler threshold levels
- Programmable TX output swing
For more information, visit point2tech.com.
Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.
