Chad Cox

November 19, 2024

San Jose, California. Point2 Technology introduced the Point2 P1B12,1 its innovative Smart Retimer system-on-chip (SoC) for AEC applications in hyperscale AI/ML datacenters. It incorporates eight-unidirectional SerDes channels with smart Clock Data Recovery (CDR)/Retimer operations that support 112G PAM4 and 56G NRZ data rates. The Point2 P1B121 is designed for low-power and low-latency operations in 800 gigabit (800G) and 1.6 Terabit (1.6T) Active Electrical Cables (AECs). At 3 nanoseconds (3ns), the P1B121 chip latency is 20X lower than standard DSP-based PAM4 Retimers.


 

November 14, 2024

On this episode of Embedded Insiders, Editor-in-Chief, Ken Briodagh, sits down with Patrick Soheili and Kevin Donnelly of Eliyan to highlight the company's new Chiplet Interconnect PHY at 64Gbps in 3nm Process. The multi-die interconnect evolution marches on and Eliyan is getting a lot of attention for its ability to deliver performance and bandwidth like this in either standard or advanced packaging.