Siemens Veloce proFPGA CS AI Chip Delivers Verification to Trillion‑Cycle Scale
April 13, 2026
News
Siemens, in collaboration with NVIDIA, publicized that its Veloce proFPGA CS hardware-assisted verification and validation system is enabling the efficient creation of enhanced designs by running and capturing trillions of verification cycles, prior to first silicon availability.
The collaboration utilizes both Siemens’ Veloce proFPGA CS scalable hardware architecture and NVIDIA’s performance-optimized chip architecture.
“NVIDIA and Siemens are partnering in many areas, most recently in advancing hardware-assisted verification methodologies in general and FPGA-based prototyping in particular, to adapt to the verification and validation demands presented by highly complex AI/ML SoCs,” said Jean-Marie Brunet, senior vice president and general manager, hardware assisted verification, Siemens Digital Industries Software. “Veloce proFPGA CS is addressing these challenges by combining a highly flexible and scalable hardware architecture with an advanced, easy-to use implementation and debug software flow, enabling customers to always have the optimal solution for single-FPGA IP validation as well as for multi-billion gate chiplet designs.”
For more information, visit siemens.com.
Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.
