Agile Analog Receives Its First Chinese Licensee for Its Analog IP

By Chad Cox

Associate Editor

Embedded Computing Design

June 10, 2022


Agile Analog Receives Its First Chinese Licensee for Its Analog IP

Agile Analog has signed its first licensee in China. “We opened our APAC regional sales and engineering office in January this year,” said Barry Paterson, Agile Analog’s CEO. “We thought that there would be a big demand for our unique analog IP solutions in the Asia-Pacific region and so we are delighted to have signed our first license for the region in just a couple of months. Key to the deal is us having local support for the customer to provide immediate answers to any engineering questions.”

In its new SSD Controller chip, the customer will use a set of Agile Analog IP. Bandgap Voltage Reference, Power On Reset, Digital Temperature Sensor, and IR-Drop Detector are all included. “Having these in a ready-to-use, drop-in form that exactly meets the required specifications enabled the customer to shorten the time to market compared to alternative solutions, which have to be custom made,” added Lisa Yang, who heads up the APAC operations. “Our ability to shortening product development times makes a huge difference in today’s competitive market, particularly in China where the competition with rivals is fierce. BOM costs is another area where we help customers as we can bring analog functions, which are normally handled by discrete components, onto the ASIC to save costs.”

Traditionally, analog IP blocks had to be manually redesigned for each application and process technology, but Agile Analog has developed a unique method for automatically generating analog IP that precisely meets the customer's specifications and process technology. It's called Composa, and it employs tried-and-true analog IP circuits from the company's Composa library. For the first time, the digital IP design-once-and-reuse-many-times model now applies to analog IP. Because the analog IP circuits in the Composa library have been extensively tested and used in previous designs, and are fully validated every time they are generated, they provide a comparable level of reassurance to the digital IP world.