RC Oscillator IP Released by Agile Analog
July 13, 2022
Agile Analog has made its new RC Oscillator IP available for purchase. This is the first in a new family of analog IP blocks that the company is introducing to make it easier to integrate analog circuits onto ASICs.
The agileOSC RC is built on a traditional architecture that enables frequency trimming to eliminate the effects of process variation. It can also be set up as a Free Running Clock (FRC), which is useful when a high accuracy clock is not required. It has a frequency range of 20 KHz to 100 MHz and an accuracy of up to +5% with a typical start-up time of 10 us. It has a low power consumption of 100 uA at 10 MHz, which is significantly less than that of an equivalent discrete analog component and demonstrates the advantage of integrating analog circuits onto the main chip.
Traditionally, analog IP blocks had to be manually redesigned for each application and process technology, but Agile Analog has developed a novel method for automatically generating analog IP that precisely meets the customer's specifications and process technology. It's called ComposaTM, and it employs tried-and-true analog IP circuits from the company's Composa library. For the first time, the digital IP design-once-and-reuse-many-times model now applies to analog IP. Because the analog IP circuits in the Composa library have been extensively tested and used in previous designs, as well as being fully validated every time they are generated, they provide a similar level of reassurance to the digital IP world's'silicon-proven.
All the major foundries are supported including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.
“These form part of the library of analog IP circuits that our automatic solution generator, Composa™, uses to create IP blocks that exactly match the requirements of customers,” explained Barry Paterson, Agile Analog’s CEO. “Their modular design means that they can be combined together to form sub-system solutions speeding up design times and reducing risk as they have all been thoroughly tested and verified.”
For more information, visit agileanalog.com.