The new working groups will build from progress in the SIL2LinuxMP and Real-Time Linux projects to help bridge gaps between the safety standards and Linux development ecosystems.

As SEGGER strengthens its position within the RISC-V instruction set architecture, the company announced its J-Link probes deliver support for the new SiFive Insight debug/trace solution.

The Learn Inventor kit is designed around one of the first commercially available RISC-V SoCs, the SiFive FE310-G003. That chip is built around SiFive?s E31 Core Complex.

Use of SiFive?s RISC-V Core IP Enables Low Power AI IoT Edge and End Point Devices.

SiFive, a provider of RISC-V core IP, recently announced its Freedom Aware (FA) family of SoC templates as well as a strategic development partnership with QuickLogic.

Company founders and executives to discuss current state of silicon in the cloud, embedded software applications and more.

Inventors of RISC-V and developers of its first Linux-compatible core wrap up 2017 with upsurge in evaluations of industry's most widely adopted RISC-V IP