Embedded Computing Design’s Road to embedded world will highlight a host of embedded suppliers who will be showcasing their latest products and technologies at embedded world, April 9th to 11th in Nuremberg, Germany. embedded world is the largest global gathering of its kind. Check back regularly to see where the Road to embedded world takes us.

Monheim am Rhein, Germany – SEGGER added a comprehensive instruction set simulator to the latest version of its Embedded Studio for ARM. The announcement follows the recently added compiler, linker, and runtime support for ARM64 enabling users to generate and debug ARM64 programs for devices like Cortex-A53, Cortex-A57, and Cortex-A72.

SEGGER released its revised Embedded Studio including source code and on-demand design of the integrated C runtime library, emRun, and C++ library, emRun++. "Embedded Studio automatically fine-tunes emRun and emRun++ for size-optimized code or speed-optimized code or a balance of both, to fit the needs of most developers,” says Rolf Segger, founder of SEGGER.

Monheim am Rhein, Germany. For the possibility to see and operate an integrated system vis USB, SEGGER announced its emVNC-Server (Virtual Network Computing). The general use of USB allows for the emVNC-Server to be integrated simply by connecting into an active interface opening it up to an abundance of options.

Monheim am Rhein, Germany – The entire E-Series of SiFive RISC-V cores with the BTM trace module are now supported by SEGGER’s J-Trace PRO with streaming trace, Live Code Profiling, and Live Code Coverage.

Monheim am Rhein, Germany. SEGGER’s J-Trace PRO, USB 3.0, for E-Series SiFive RISC-V cores offers streaming trace, Live Code Profiling, and Live Code Coverage for real time data processing for addressing runtime hotspots and opportunities to enhance them. Included are J-Link’s features such as high-performance flashloaders, up to 4 MB/s download speed, and an unlimited number of breakpoints in the flash memory of MCUs.

Monheim am Rhein, Germany – October 10th, 2022 – SEGGER announced native J-Link debug probe support for select use cases with the Cadence Tensilica Processor IP. The Cadence Tensilica cores supported in the first implementation phase are the Tensilica Xtensa LX7 CPU, a number of Tensilica HiFi DSPs (HiFi 4, HiFi 3z, HiFi 3, and HiFi 1), and also the Tensilica Fusion F1 DSP.