Laguna Hills, California. BrainChip Holdings Ltd released information it is now integrating Andes Technology’s RISC-V cores with its NPUs. According to the press release, the companies will exhibit BrainChip’s Akida AKD1500 on Andes’ QiLai Voyager Board and AndesCore AX45MP 64-bit multicore CPU IP at Andes RISC-V Con 2025 in San Jose, Calif. April 29 and in Hsinchu, Taiwan June 10.

Winners have been chosen based on a 15-point rubric that considers solutions’ Design Excellence (5 points), Relative Performance (5 points), and Market Impact/Disruption (5 points).

AndesCore™ N25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications. Approved based on the functional safety assignments of a Safety Element Out-of-Context (SEooC), which includes the ISO 26262 compliant development process and the qualitative approach with respect to hardware safety analysis, N25F-SE is certified to be used in safety-related applications.

Hsinchu, Taiwan and Uppsala, Sweden. Andes Technology and IAR collaborated on  ILITEK’s Touch and Display Driver Integration (TDDI) SoC, ILI6600A. The SOC integrates the Andes N25F-SE ISO 26262 certified V5 RISC-V CPU core, and the IAR certified Embedded Workbench toolchain for RISC-V.

Andes Technology will highlight its innovative embedded processors and SoC platform solutions that provide complete architecture in which the software development tool chains, virtual SoC platforms, hardware development platforms, and Andes IP Cores are connected to develop in-house SoC and system solutions. Andes will be showcasing its IP solutions in booth 4A-620 at embedded world 2023.

Hsinchu, Taiwan. Join Dr. Charlie Su, President and CEO of Andes, during his annual Andes Webinar for information on the newest adoptions of RISC-V solutions and Dr. Su’s prognosis on the future of RISC-V integrations. His speech, "Expanding the RISC-V Horizon and Beyond" focuses on the functional capabilities of its N25F-SE. The N25F-SE is certified compliant within the ISO 26262 (Parts 2, 4, 5, 8 and 9) functional safety standards and ASIL B (Automotive Safety Integrity Level B) for automotive applications.

Uppsala, Sweden. IAR Systems revealed its complete support for the recent availability of IAR Embedded Workbench meant for RISC-V for the CoDense expansion of Andes Technology’s AndeStar V5 RISC-V processor. The CoDense in AndeStar V5 is intended for the compression of code with standard RISC-V instructions. CoDense in AndeStar V5 is an Andes-extended feature for code size compression on top of the RISC-V standard instructions.