IAR Embedded Workbench for RISC-V Utilizes Andes' CoDense For Code Compression
November 18, 2022
Uppsala, Sweden. IAR Systems revealed its complete support for the recent availability of IAR Embedded Workbench meant for RISC-V for the CoDense expansion of Andes Technology’s AndeStar V5 RISC-V processor. The CoDense in AndeStar V5 is intended for the compression of code with standard RISC-V instructions. CoDense in AndeStar V5 is an Andes-extended feature for code size compression on top of the RISC-V standard instructions.
“Thanks to our close cooperation with Andes, we provided early support for the AndeStar™ V5 DSP/SIMD and Performance extensions and now full support for Andes CoDense™, enabling code size compressions on top of RISC-V C-extension,” said Anders Holmberg, CTO at IAR Systems.
Version 3.11 is supplied with a “P” extension 0.9.11 support (Standard Extension for Packed-SIMD Instructions), SMP (Symmetric Multi-Processing) and AMP (Asymmetric Multi-Processing) multicore debugging, IAR Build, and IAR C-SPY Debug additions. The C-SPY Debugger offers designers complete management of the application in real-time by applying complex breakpoints, profiling, code coverage, timeline with interrupt, and power logging.
Embedded code analysis tools safeguards compliance with individual standards like MISRA C (2004 and 2012), Common Weakness Enumeration (CWE), and CERT C Secure Coding Standard. The IAR Embedded Workbench for RISC-V includes a safety report and guide for ten unique standards applying to applications including automotive or industrial.
Dr. Charlie Su, President and CTO of Andes Technology believes, “CoDense increases the code density significantly by double digits and is very welcome in MCU or IoT applications. We look forward to the competitive combination of IAR Embedded Workbench with AndeStar V5 RISC-V extensions with up to 30 percent higher performance made available to the RISC-V community.”
For more information on the IAR Embedded Workbench for RISC-V, visit iar.com/riscv.