Join Dr. Su at the Annual Andes Webinar

By Chad Cox

Associate Editor

Embedded Computing Design

January 13, 2023

News

Hsinchu, Taiwan. Join Dr. Charlie Su, President and CEO of Andes, during his annual Andes Webinar for information on the newest adoptions of RISC-V solutions and Dr. Su’s prognosis on the future of RISC-V integrations. His speech, "Expanding the RISC-V Horizon and Beyond" focuses on the functional capabilities of its N25F-SE. The N25F-SE is certified compliant within the ISO 26262 (Parts 2, 4, 5, 8 and 9) functional safety standards and ASIL B (Automotive Safety Integrity Level B) for automotive applications.

Dr. Su says, “Andes has developed a wide range of AndesCore processors, from driving cost sensitive MCUs to accelerating datacenter AI/ML computations. We are excited to announce our first safety-enhanced AndesCore® the N25F-SE based on the most popular and mature CPU IP family, the 25-series."

The AndesCore N25F-SE leverages a 32-bit RISC-V CPU core with typical IMACFD extensions. The implementation of the Andes V5 extension protocols optimize performance with a reduction in code. The platform utilizes a 5-stage pipeline with optimized frequency. With the accommodating interface, certified flexible options, and compact design, development teams no longer have a threshold of one fixed CPU configuration for automotive processor cores.  

(Andes Interview at RISC-V Summit 2022)

“Andes is the first RISC-V CPU vendor certified, for the development process of automotive processor cores, to be compliant with ISO 26262 standards up to ASIL D in 2020. With the certified development process in place, we formally started our functional safety roadmap to deliver at least one ISO 26262 compliant core every year to cover all segments of performance and features,” continued Dr. Su.

You may register for the webinar here.

For more information, visit andestech.com.

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