ARIES Embedded and Emdalo Technologies collaborated to enhance embedded modules centered on Microchip's PolarFire SoC architecture. ARIES designed the M100PF and M100PFS system-on-modules (SoM) delivering effective embedded ecosystems for power computations in applications such as smart embedded vision, industrial automation, communications, and IoT.

RISC-V Summit, San Jose. Microchip worked with NASA and the aerospace and defense industry to develop a RISC-V-based High-Performance Spaceflight Computing (HPSC) processor that is being presented at the RISC-V Summit. Microchip is also promoting its PolarFire 2 FPGA silicon platform and RISC-V-based processor subsystem with a software suite roadmap at the Summit.

CHANDLER, Arizona— Microchip Technology’s recently announced LAN8840 and LAN8841 Gigabit Ethernet transceiver devices are a standard-based solution designed to provide critical process synchronization to developers of industrial-grade networking solutions, such as process automation applications.

CHANDLER, Ariz.,— Microchip Technology is introducing its first Arm Cortex®-M4F-based PIC microcontroller (MCU) family designed to combat wireless connectivity design challenges with the integration of Bluetooth Low Energy functionality, which can be directly integrated into a systems’ components. 

When does a cyber security problem become a physical security problem? Or stated differently, when do semiconductors have to have built-in tamper detectors?

CHANDLER, Ariz., Microchip Technology announced a new family of Terabit-scale Ethernet PHYs (physical layer), the META-DX2+, designed to provide OEMs the ability to double router and switch system capacities with 112G PAM4 connectivity for 800G ports, and support for encryption and Class C/D precision timing.

Microchip Technology achieved the first qualification milestone with its RT PolarFire FPGA, enabling designers to begin assembling spaceflight systems that take advantage of this FPGA's computing and connectivity throughput and its lower power consumption and immunity to configuration Single Event Upsets (SEUs) compared to SRAM-based FPGAs.