Barcelona, Spain. Semidynamics released information that UPMEM has selected Semidynamics as its core source for its next generation of LPDDR5X Processing in Memory device. By incorporating the Tensor Unit and Gazillion optimizer, the RISC-V architecture enables efficient integration of any AI or LLM models.

Barcelona, Spain. Semidynamics is now recruiting various engineers of all levels at its Barcelona headquarters. The company's workforce has expanded from 40 employees to 90 this year, with a target of 120 by early 2025.

Barcelona, Spain – 5 April 2024. Semidynamics, the European RISC-V custom core AI specialist, has announced its ‘All-In-One AI’ IP that is designed for super powerful, next generation AI chips and algorithms such as transformers. Currently, AI chip designers use the approach of integrating separate IP blocks next to the system CPU to handle the ever-increasing demands of AI. Semidynamics has taken a revolutionary approach of a unified solution combining RISC-V, vector, tensor and Gazzillion technology so that AI chips are now easy to program and scale to whatever processing power is required.

Campbell, California. Arteris, Inc. and Semidynamics are collaborating to enhance the next generation of electronic components for artificial intelligence (AI), machine learning (ML) and high-performance computing (HPC) applications. The agreement sees the interoperability between Semidynamics' Atrevido and Avispado 64-bit RISC-V processor IP cores and Arteris’ Ncore cache coherent network-on-chip (NoC) system IP.

Barcelona, Spain. Semidynamics and SignatureIP are collaborating to incorporate respected technologies for a completely assessed multi-core RISC-V environment and CHI interconnect for innovations in chip development for AI and ML applications. The solution utilizes SignatureIP’s Coherent NoC, designed to be scalable with the inclusion of a transport layer for chiplet communication and acts as an ordered file system with support for home-node resource group.

Barcelona, Spain. Semidynamics released its 64-bit flexible 4-way Atrevido 423 RISC-V core delivering double the instructions than the 2-way, 223 core. More functioning units are utilized increasing the IPC (instructions-per-cycle). The processor core can be utilized in two ways, as a coherent core sharing memory with others via CHI (Coherent Hub Interface) NoC (Network on Chip), or an incoherent core operating independently and uses an AXI interface for communication.

Barcelona, Spain. Semidynamics delivers a fully customizable Vector Unit integrated into 64-bit RISC-V cores able to run up to 2048b of computation per cycle for large data transmissions. The unit follows the RISC-V Vector Specification 1.0 and adds many features to fit user requirements.