Semidynamics Released its 4-way Atrevido 423 RISC-V Core

By Chad Cox

Production Editor

Embedded Computing Design

July 28, 2023


Semidynamics Released its 4-way Atrevido 423 RISC-V Core
Image Credit: Semidynamics

Barcelona, Spain. Semidynamics released its 64-bit flexible 4-way Atrevido 423 RISC-V core delivering double the instructions than the 2-way, 223 core. More functioning units are utilized increasing the IPC (instructions-per-cycle). The processor core can be utilized in two ways, as a coherent core sharing memory with others via CHI (Coherent Hub Interface) NoC (Network on Chip), or an incoherent core operating independently and uses an AXI interface for communication.

Roger Espasa, Semidynamics' CEO, said, "The Atrevido 423 is particularly well suited for applications that require massive amounts of data. It shines when the data required cannot fit in memory hierarchy levels that are closer to the core (such as L1, L2 or even L3) by tolerating very large latencies without compromising on throughput thanks to our Gazzillion misses technology. This can handle up to 128 simultaneous requests for data and track them back to the correct place in whatever order they are returned. Gazzillion allows the core to access memory hierarchy levels far away from the core without an impact in bandwidth or throughput.”

The 423 RISC-V core features an advanced TLB (Translation Lookaside Buffer) and MMU (Memory Management Unit) and added support for different page formats such as SV39/48/57. To aid in efficiency, the out-of-order core is available with numerous RISC-V extensions. One such instance is that the processor core can be arranged with the Semidynamics’ in-house Vector Unit with complete support for the latest RISC-V vector spec.

Additional Extensions Include:

  • bit manipulation
  • crypto
  • single-precision FP
  • double-precision FP
  • half-precision FP
  • bfloat16

"Customers for these kinds of state-of-the-art cores want to have unique solutions with their own special secret sauce built," explained Espasa. "We are unique in offering Open Core Surgery where we open up the core to insert custom instructions within it. This is unique as other companies' cores are only configurable from a set of predetermined options. This completely protects the customer's ASIC from copying and protects its multi-million-dollar investment in the new ASIC. It also means that it is optimized for Power, Performance and Area with no unnecessary overheads or compromises."

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*Editor’s Note: The cores are process agnostic with versions already being supplied down to 5nm.

Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.

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