RISC-V Environment and CHI Interconnect for AI and ML Applications

By Chad Cox

Production Editor

Embedded Computing Design

October 04, 2023


Image Credit: SignatureIP

Barcelona, Spain. Semidynamics and SignatureIP are collaborating to incorporate respected technologies for a completely assessed multi-core RISC-V environment and CHI interconnect for innovations in chip development for AI and ML applications. The solution utilizes SignatureIP’s Coherent NoC, designed to be scalable with the inclusion of a transport layer for chiplet communication and acts as an ordered file system with support for home-node resource group.

Kishore Mishra, SignatureIP’s CTO, added, “Semidynamics revolutionized the 64-bit RISC-V processor with cores that are fully customizable using its ‘Open Core Surgery’ approach. This goes deep into the core and is not the tweakable approach typically found in IPs. Combining our technologies now enables multi-core chip designs to be created on this fully coherent RISC-V/CHI platform and then prototyping on an FPGA to demonstrate the integrated performance. We have fully tested them together to ensure compatibility and minimization of verification time.”

With SignatureIP’s inoculator.ai tool, a physically-aware NoC is generated with automation support.

“SignatureIP’s C-NoC CHI interconnect solution makes it very straightforward to lay out the Network on Chip (NoC) for multiple cores on a chip using our mature, proven technologies which minimizes risks and accelerates time to market,” ends Semidynamics’ CEO and founder, Roger Espasa.

For more information, visit signatureIP.ai and semidynamics.com.

Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.

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