Munich, Germany. Codasip generously donated its newly developed Software Development Kit (SDK) for CHERI to the communal CHERI Alliance, and makes the SDK freely available for download on GitHub. CHERI (Capability Hardware Enhanced RISC Instructions) is an innovative security technology established by the University of Cambridge in collaboration with SRI International.

Writing my Exploited articles and traveling to our next stop, my head was brought to Sun Tzu, and his quote from The Art of War, “The art of war is of vital importance to the State. It is a matter of life and death, a road either to safety or to ruin.” Sounds drastic but let us think about all the data floating around ready for anyone with a means to just snatch it.

Codasip, along with Intel, are providing educational tools for future RISC-V developers in the form of undergraduate and graduate curriculum combing assets such as Codasip RISC-V IP cores, Codasip Studio development environment, and Intel's FPGA platforms. The provided lessons use a project-based RISC-V learning opportunity.

RISC-V Summit, San Jose. Codasip announced its SecuRISC5 for reliable custom compute that utilizes reference designs merging Codasip IP and third-party technology. The recently launched Codasip Labs¹ will recognize openings where SecuRISC5 will be attentive, a hub, and a coordinator of pan-industry collaboration.

Munich, Germany – Codasip announced that the organization, Codasip Labs, is now positioned as an innovation hub within the company, supporting the development and commercialization of security, functional safety, and AI/ML applications to foster cooperative research between Codasip and its partners, customers, and academia.

Munich, Germany – The Codasip University Program has joined Intel Pathfiner for RISC-V in a collaboration to bring Codasip RISC-V IP cores, the Codasip Studio development environment, and Intel's FPGA platforms to undergraduate and graduate courses. Codasip's University Program is currently working with a number of universities, in light of the expansion of Intel’s Pathfinder ecosystem, to provide students with access to Codasip Studio and project-based RISC-V assignments.

Munich, Germany; Seoul, South Korea. Codasip shared news the that SiliconArts has embraced Codasip 7-series RISC-V processors with Codasip Studio customization tools. Codasip’s RISC-V processor IP combined with SiliconArts ray tracing GPUs are designed for complete optimization of demanding graphic applications. Ron Black, CEO, Codasip, commented, "It's becoming extremely difficult to make performance gains from scaling semiconductors to smaller nodes. RISC-V combined with the customization capabilities of Codasip Studio enable our customers to make significant performance gains."