Codasip and Intel Combine Powers for Future RISC-V Developers

By Chad Cox

Associate Editor

Embedded Computing Design

January 17, 2023


Image Provided by Codasip

Codasip, along with Intel, are providing educational tools for future RISC-V developers in the form of undergraduate and graduate curriculum combing assets such as Codasip RISC-V IP cores, Codasip Studio development environment, and Intel's FPGA platforms. The provided lessons use a project-based RISC-V learning opportunity.

Vijay Krishnan, General Manager, RISC-V Ventures from Intel, commented, "Codasip has put together a program that comprehends the needs of universities worldwide. By extending our collaboration with Codasip to include the education segment, we hope to enable the next generation of RISC-V developers on an accelerated timeline."

Codasip’s new educational tools will begin implementation in the fall. The courses will leverage Intel Pathfinder for RISC-V qualified FPGA development boards. Graduate studies are centered on System-On-Chip curriculum while undergraduates learn High-Level Synthesis (HLS) & Verilog curriculum assignments requiring lower price points.

Keith Graham, Vice President of University and Customer Experience Program, Codasip, said, "The addition of Intel's FPGA platforms into Codasip's computer architecture project-based assignments will further boost our three University Program Pillars; preparing the next generation of researchers, training the next generation of engineers, and developing solutions to solve tomorrow's technological challenges."

The Intel Pathfinder for RISC-V facilitates framework discovery with exploration of differing configurations and combinations of IP. It offers a standard environment for accessing RISC-V and peripheral IP that collaborates with the FPGA boards.

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