Microchip is packing up in Chandler, Arizona and will start its trip to the RISC-V Summit in Santa Clara, California, November 7^th and 8^th, 2023, and November 6 being Member Day. Microchip will be demonstrating its market leading FPGA solutions for the intelligent edge and how it leverages the RISC-V ISA to design heterogenous processing architectures for non-proprietary instruction set architectures.

Qualcomm Technologies, Inc. will be bringing a RISC-V based wearable platform to Wear OS by Google. The framework is expected to expand the products compatible within the environment. The platform will leverage low-power high-performance custom computers.  

On this episode of Embedded Insiders, Randy Fish, director of product line management for the Silicon Lifecycle Management family at Synopsys, highlights how automotive engineers can benefit from the SLM on-chip monitoring and analysis process.

Barcelona, Spain. RISC-V International will be highlighting the latest RISC-V innovations across industry and the research community during the first ever RISC-V Summit Europe. The summit will be in Barcelona during the 5^th and 9^th of June 2023.   

I remember being in kindergarten and watching the Challenger rip apart 73 seconds after launch. There were two classes in the room that day watching the TV in shock, and me, with the wonder of what is really out there. Haruki Murakami in Kafka on the Shore sums up perfectly how I perceive space. “Beyond the edge of the world there’s a space where emptiness and substance neatly overlap, where past and future form a continuous, endless loop. And, hovering about, there are signs no one has ever read, chords no one has ever heard.”
 

RISC-V International announced its first four specification and extension approvals of 2022 – Efficient Trace for RISC-V (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V Unified Extensible Firmware Interface (UEFI) specifications, and the RISC-V Zmmul multiply-only extension.

Renesas Electronics Corporation's RZ/Five employs the Andes AX45MP, based on the RISC-V CPU instruction set architecture (ISA). The RZ/Five augments Renesas’ previously available Arm® CPU core-based MPUs, expanding customer options and providing more flexibility in the product development process.