SNUG 2023: Can AI Transform EDA’s Engineering Shortage into a Surplus?

By Brandon Lewis


Embedded Computing Design

March 29, 2023


The engineering shortage has been a topic of conversation for years, and while the industry talks the average age of electronics engineers keeps increasing. The high-tech sector once again finds itself at a crossroads of doing more with less or innovating – albeit this time with the goal of attracting fresh new talent to its ranks.

If you think the lack of engineers is a problem in other areas, consider the electronic design automation (EDA) space. It’s an esoteric field with just a few key suppliers and an extremely high barrier to entry for both individuals and startups. At the same time, without EDA-enabled design, verification, testing, and manufacturing, the microprocessor on your bench right now probably wouldn’t be there.

As we approach the end of Moore’s law, EDA will be an increasingly vital part of the equation to achieve better performance and lower power consumption in smaller area. But young engineers who would have found themselves creating EDA tools, using them to develop new chips, or building systems with semiconductors enabled by EDA thirty years ago keep winding up in cubicles at large hyperscalers – ironically, some of the biggest users of EDA technology in the creation of advanced data center chipsets.

The world needs EDA, but it also needs engineers. So where do we go from here? Addressing the EDA Shortfall with Smarter Automation

Eerily, just as the engineering shortage is reaching a fever pitch the AI industry has exploded. Everywhere from ChatGPT to autonomous robots to yes, even chip design, AI is revolutionizing not only the systems we build but also the ways we build them. EDA is no exception, where companies like Synopsys are putting it to use in optimization tools that offload repetitive chip design exploration, verification coverage, regression analytics, and test program generation tasks.

These applications of AI are the focus of the Synopsys’ 2023 user group conference, SNUG. The AI Synopsys is putting to use in solutions like their (design space), (functional verification), and (silicon test) stack – collectively, – isn’t the open-ended, unsupervised AI you get with ChatGPT, nor is it the insatiable data experimentation of vision algorithms. Instead, the company relies on reinforcement learning to analyze and optimize customer designs for power, performance, and area (PPA) at lower cost and faster (in some cases, months faster) than humans working towards the same goals (Figure 1).

Figure 1. Synopsys’ design space optimization tool uses reinforcement learning against customer chip designs to realize optimizations far in advance of what it would take human engineers months to achieve.

But instead of replacing engineers outright, reinforcement learning applied in tools like analyzes the PPA of an implementation across logical and physical domains by optimizing the whole design across a dizzying number of choices. It does so at a scale that’s just not achievable by human engineers, and the results don’t disappoint: users are reporting 3x productivity enhancements, 15% power reductions, and greater than 100 MHz frequency improvements while shaving weeks off their product development times.

Lead customers have already leveraged in more than 100 production tapeouts, while other AI-enabled Synopsys tools are also helping industry partners cut cost and improve time to market. Renesas, for instance, is using the RTL examination engine in Synopsys VCS to realize a 10x acceleration in deep bug hunting and coverage closure and up to 30% increases in overall IP verification productivity in complex designs.

Add into automatic test pattern generation (ATPG) to account for defect coverage, pattern count, and run time during the silicon test process, and you have an end-to-end AI-powered EDA stack.

Cutting Cost, Time to Market, and … Jobs?

The cost, time to market, and performance optimizations of “EDAI” are becoming more of a necessity than a luxury, and are poised to reframe the conversation around chip design productivity as the technology matures. As any good AI does, the reinforcement learning technology underpinning continues to improve as it trains on unique data sets over time, which means the gains chip designs experience today are bound to increase in the future.

But what about the conversation around the engineering shortage?

As a cloud-based offering, is easily accessible and integrates with existing RTL-to-GDSII flows without interrupting the chip design process. It’s not a one-to-one replacement for a chip designer, but it frees them to pursue more creative endeavors like adding features or developing derivatives while still meeting time-to-market targets.

As you can see in from the customer feedback shown in Figure 2, it’s a force multiplier for engineers. While it won’t serve as a one-to-one replacement for chip designers, AI solutions like augment the chip designers to the point that they become more than just a single designer – they essentially become a design team.

As industry continues to contend with an engineering shortage no one is sure will end, all sectors will need to adopt an AI-driven approach to productivity that Synopsys is delivering into the EDA space with It’s about getting the absolute maximum from your resources today.

And tomorrow, it will likely help lower barriers to entry for engineers so more of us can take part in chip design – or whatever flavor of electronic design you’re in – than ever before.

Figure 2. AI like Synopsys is poised to become a force multiplier for chip designers faced with fewer resources and more demanding delivery timelines.


Brandon is responsible for guiding content strategy, editorial direction, and community engagement across the Embedded Computing Design ecosystem. A 10-year veteran of the electronics media industry, he enjoys covering topics ranging from development kits to cybersecurity and tech business models. Brandon received a BA in English Literature from Arizona State University, where he graduated cum laude. He can be reached at [email protected]

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