Filling the Forgotten Mid-Range FPGA Segment

By Rich Nass

Executive Vice President

Embedded Computing Design

December 06, 2022


Filling the Forgotten Mid-Range FPGA Segment

Sometimes problems are so obvious that you don’t see them. That was the case with the mid-range FPGA market and, frankly, until it was pointed out to me, I wasn’t aware that the problem even existed.

What I’m referring to is the fact that most (all?) of the latest developments in the FPGA space have either touted super high performance or super low power consumption. That leaves out a segment—a huge segment.

If you’re designing for industrial applications, for example, performance is important, but you’re generally not pushing against the boundaries. And the same is true for power; while we all want to maintain a power spec that’s low, it’s not at the top of the list for many developers.

The combination of the two specs, along with an enviable package size and a cost that is sure to remain within budget was the target for the Lattice Semiconductor design team, and they seem to have hit the mark with the release of the Avant family of FPGAs, with logic-cells arrays ranging from 200k to 500k.

While other vendors do have products that fit this category, those products typically aren’t designed for the category from the ground up. They will take a higher end FPGA and reduce the log-cell count to fit the midrange space, or take one at the lower end and attempt to spruce it up to reach the higher level. Called the “waterfall effect,” it’s clear when you dive into the specs that the mid-range was not the real focus.

The Avant platform fits the mid-range bill in terms of low power, small package size, high DSP performance, support for the latest memory technologies, and next-generation security features. With supported clock rates range up to 350 MHz for the FPGA fabric, 625 MHz for embedded RAM blocks, and DSP multiply/accumulate blocks, potential applications for the family include networking controllers, PLCs, Edge computers, machine vision, and industrial robotics. Thanks to the inclusion of 25 Gbit/s SERDES and PCIe Gen4, it can also be used for automotive networking and software-defined radio. And the DSP performance can handle the latest AI algorithms.

On the security front, Avant includes a wide range of capabilities, such as AES256-GCM, ECC, RSA, anti-tamper, and a physically unclonable function (PUF). Hence, configuration and user-data can be encrypted and authenticated. Soft error detection and correction ensure that environmental effects that cause soft errors are detected quickly so appropriate actions can be initiated. User-mode security is implemented through hardened crypto engines accessible as IP blocks embedded in the FPGA fabric

In terms of the key specifications, Lattice claims that its Avant platform provides:

  • up to 2.5X lower power than similar class competitive devices
  • up to 2X faster throughput than similar class competitive devices (with less power)
  • up to 6X smaller packages compared to similar class competitive devices

Another important factor is that the new FPGAs are based on the company’s existing software platform, significantly reducing the learning curve for developers and ultimately reducing the time to market. Sampling has commenced and production quantities will roll out throughout next year.

Richard Nass’ key responsibilities include setting the direction for all aspects of OSM’s ECD portfolio, including digital, print, and live events. Previously, Nass was the Brand Director for Design News. Prior, he led the content team for UBM’s Medical Devices Group, and all custom properties and events. Nass has been in the engineering OEM industry for more than 30 years. In prior stints, he led the Content Team at EE Times,, and TechOnLine. Nass holds a BSEE degree from NJIT.

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