Third Party IP Block Licensing from Sondrel
November 07, 2024
News
Sondrel has made its in-house IP available for licensing including a suite of IP blocks for standard SoC management that are designed to operate start-up of devices, clock and reset control, and power domain handling. The SoC Management Suite is divided into three parts, the PMU (Power Management Unit, the URG (Universal Reset Generator), and the UCG (Universal Clock Generator).
PMU:
- Start-up of the SoC out of reset
- Software control for switchable digital domains to be powered up and down
- Software with control over the reset tree (once start-up is complete)
- Mitigating action as required and acting as the Error Detection Unit
- Creating reaction to functional safety faults detected within the system (putting the system into ‘Safe-Mode’)
The PMU can cooperate with a URG to regulate the resets via Sondrel’s Power Down Controller Interface control bus. The Universal Reset Generator (URG) is an SoC IP that is accountable for coordinating on-chip reset. A Reset-tree management offers support for the increasing complexity of logic within an SoC. The purpose of the URG is to have a single, universally configured block to deliver correct sequencing of resets to the entire system.
The reset state can be changed by events originating from various sources, such as:
- A hardware trigger: Examples include: a system reset pin, a watchdog timer IP, a security IP, a CPU exception flag
- A software-driven event: i.e. a driver deciding that IP is in an unknown state.
- The Power Management Unit, which must manage resets in tandem with power island voltage controls to facilitate power state transitions.
The Universal Clock Generator (UCG) is a lightweight and scalable SoC IP that coordinates on-chip clock management while supporting:
- Several clock sources and references as input to a generic crossbar
- Up to 128 clocking channels (independently software configured)
- Clock dividers on each channel and a clock enable (glitch-free implementations)
- Observation clocking points
- DFT (Design For Test) control of clock outputs
- Safety mechanisms (identifying a failed default clock and relaying the fault to the system
Oliver Jones, Sondrel’s CEO, said, “For years, we have been creating IP blocks for our internal use when we design custom chips. We are now making these available for licensing by third parties. They are silicon proven as we have already successfully used them in designs for our customers. We had to create these IP blocks as there was nothing commercially available to deliver the functions and performance that we required for the advanced ultra-complex custom chips that we design. Some are slightly unusual but that is the very reason why we created them. If we needed them for a design, then others will too.”
For more information, visit sondrel.com.
Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.
