ECD: What emerging trends and challenges do you see in embedded design?

OR-BACH: Dimensional scaling has reached a pivotal point of escalating development costs and interconnect Resistance-Capacitance (RC) delays. Quoting IBS, “At 14 nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically.” Very few designs can be financed at such high costs.

RC delays are a key bottleneck in today’s chips, and the ratio of interconnect RC delay to transistor delay has been growing by about an order of magnitude for every two nodes of scaling. A GPU made with 28 nm CMOS, for instance, requires several times more energy for communicating data than for computation.

We are now seeing a trend to develop 3D IC technology, such as the Hybrid Memory Cube introduced by Intel, Micron, and others. As well, TSMC and GLOBALFOUNDRIES have announced they are establishing manufacturing lines for 3D IC. We believe that these trends will accelerate with the adoption of monolithic 3D technology as an alternative for dimensional scaling.

ECD: Which engineering specialties are most valuable to your company, and are they difficult to find?

OR-BACH: Our company is about reinventing the semiconductor industry from 2D into 3D. We develop innovative flows that utilize well-known semiconductor processes to construct devices with multiple transistor layers. Our team must accomplish what was once considered unachievable while using proven processes and equipment. Finding engineers with a broad yet deep process knowledge, in addition to possessing an innovative bent and the ability to think without a “box,” is difficult.

ECD: What is your assessment of the demand for ubiquitous connectivity, and how does it affect your product development plans?

OR-BACH: In the next 10 years we expect to see rapid growth in wireless communication, especially in the Internet of Things. Some applications will become mission-critical, such as autonomously driven vehicles and accident-avoidance systems.

MonolithIC 3D has innovated practical technologies to process multiple tiers of circuits with vertical connectivity comparable to horizontal connectivity. The technology utilizes thin layers (<100 nm) of monocrystalline silicon so that each tier adds about 1 micron to the chip’s thickness, allowing high integration if the yield limit can be overcome. Utilizing a high density of vertical connections, we have developed methods that enable effective logic redundancy to overcome yield limitations and in-field circuit failures.

These methods are based on three primary ideas:

• Swap/replace at a logic cone granularity level.
• The redundant logic cone/block is directly above, so there is no performance penalty.
• There is negligible design effort, as the redundant layer is an exact copy of the primary layer.

Scan chain technology enables circuit testing whereby faults are identified at the logic cone level. The device controller uses this information to replace a defective logic cone by the redundant logic cone located ~1 micron above.

Building the same circuit twice, one on top of the other, allows the replacement logic cone above to repair every fault. Such a repair involves a negligible power penalty and minimal cost penalty whenever the base circuit yield is above 50 percent. This design methodology provides many additional benefits, including almost no extra design cost. Monolithic 3D technology thus can enable reliable and integrated ubiquitous connectivity.

ECD: How will embedded computing advance in the next 5-10 years?

OR-BACH: We will see growth in the area of smart connected devices that gain access to sensory information and interact with mobile users and other devices. 3D ICs will offer a new architectural paradigm, such as ultra-low-power systems and ultra-high integration, for embedded computing designs.