Best practices for RF layout in wireless SoC designs

December 01, 2016


Best practices for RF layout in wireless SoC designs

The system-on-chip (SoC) integration of wireless connectivity with microcontrollers (MCUs) is an enabling technology for connected device applications...

The system-on-chip (SoC) integration of wireless connectivity with microcontrollers (MCUs) is an enabling technology for connected device applications throughout the Internet of Things (IoT). The latest wireless SoC devices accelerate the development of high-performance networks and enable compact, low-power, and cost-effective system designs to be delivered to market in ever-shorter timeframes. Whether it is a Bluetooth connection between a wearable device and a smartphone, or a smart home application using ZigBee or Thread as the communication protocol, the underlying technology relies on radio frequency (RF) signals being transmitted and received at frequencies up to 2.4 GHz. Maximizing the performance of any wireless connection means paying close attention to the RF circuit design and particularly to board layout.

Wireless design can be challenging as the desired RF signals will often be in close proximity to unwanted RF signals, such as the MCU clock or the high-frequency signals generated by switching power supplies. Consequently, the communication range achieved by a poor design is likely to be impaired or will require higher transmit power levels to compensate, which will result in a shorter battery life for a portable device. Higher power signals can also give rise to spurious signals that may cause interference to other equipment and fail to meet standard regulatory requirements.

For these reasons, it is helpful to understand the design goals for effective wireless communication, how the circuit layout impacts these goals and, most importantly, how to extract the maximum RF performance from a design by following some simple best practices. We will explore these with reference to the specific circuit board layout for Silicon Labs’ EFR32 Wireless Gecko SoCs.

Factors that affect RF performance

The RF performance of a wireless device is critically dependent on the design and layout of the RF section of the printed circuit board (PCB). The position of the RF components in the matching network, in terms of their orientation and separation from other components, can have a significant effect on the coupling of unwanted signals. The routing and dimensions of the RF traces can be equally important as the choice of antenna used in the design. In addition, factors such as ground metallization, the routing of non-RF traces, especially the supply lines, and the nature of the PCB itself, such as board thickness, dielectric constant, and the number of layers, all play their part in the overall design. Other components mounted on the board, including MCU clock circuits and power converters, can give rise to excessive spurs in the RF spectrum causing sensitivity degradation. Therefore, it is important to employ appropriate filtering to isolate the high-frequency signals from these sources and prevent them from reaching the RF path.

To better understand how to accomplish this filtering, we first need to understand the RF circuit functions. The radio within the IC comprises a transmitter and a receiver. The goal of the transmitter (Tx) is to drive as much of the wanted signal into the antenna as possible. The use of impedance transformation between the RF IC and the load aims to maximize radiated power at the fundamental frequency and minimize any dissipated losses from harmonic and other spurious frequencies. This is achieved with a combined matching and filtering network composed of series inductors and parallel capacitors. For operation at 2.4 GHz at Tx power levels above 13 dBm, a 4-element ladder as shown in Figure 1 is recommended. When operating at lower power, a 2-element L-C network may be sufficient. In receive mode, the receiver (Rx) uses the same impedance-matching network to achieve maximum sensitivity.

[Figure 1 | A four-element transmitter-matching network for use at 2.4 GHz]

Considerations when laying out the RF section

While wireless SoC suppliers provide reference designs that have been developed to deliver the best possible RF performance, it is not always possible to copy this design as is into an end-system design due to size or form-factor restrictions. Clearly, any deviation from the reference design can impact performance. At the high frequencies involved, changes in the distances between components can introduce parasitic inductances due to the different circuit board trace lengths. A different substrate thickness or dielectric constant, or the gaps between traces, can introduce parasitic capacitances. Changing the spacing or orientation of components relative to one another can affect signal couplings, while changing component types or sizes from those recommended can also introduce different component parasitics.

Poor design choices can cause detuning of the matching and filtering network and can also detune the load of the crystal. The possible consequence of this can be a decrease in Tx output power, reduced Rx sensitivity, an increase in the level of spurious emissions, increased current consumption, and potentially a frequency offset between different boards, all of which can be observed with both conducted and radiated signal measurements.

Furthermore, problems are not necessarily confined to the RF section of the circuit board. From an RF radiation perspective, the whole PCB design must be considered since factors such as the ground plane and its size will affect the power of the transmitted signal, especially when using a monopole-type antenna. The shielding effect of the ground plane will also affect the level of radiated spurs, as will non-RF traces, and care must be taken to ensure these are kept well within EMC limits. It should also be appreciated that even a reference design used as is is not a complete application, and similar care should be exercised with respect to other circuitry on the board outside the area of the reference design.

Following best layout practices for the RF section

When it is not possible to implement a reference design exactly as is, it pays to follow a number of guidelines. Figure 2 shows example guidelines for the layout of a 2.4 GHz radio board.

Starting with the matching network, the first component should be placed as close as possible to the Tx output pin of the RF IC to reduce any detuning effect due to the parasitic inductance of an extended signal trace. The remaining matching network components should be placed close to each other to minimize any PCB parasitic capacitance to ground or further trace parasitic inductance between components. Ideally the trace width used to connect these components should be the same as the pad width, which is typically 0.5 mm for 0402-sized SMD components.

[Figure 2 | Layout of a 2.4 GHz EFR32 radio board showing key circuit areas]

The correct placement of decoupling capacitors on all supply pins is vital. The lowest value bypass capacitors filter out signals around the fundamental Tx/Rx frequencies and need to be placed closest to the IC pins with good grounding using multiple vias to the ground plane. Bypass capacitors with values around 100 nF will suppress clock signals in the range of tens of megahertz, which could otherwise be up converted within the chip, causing unwanted spurs around the carrier frequency. The largest value capacitors are intended to filter out the interference coming from switching power supplies, which will typically be around several hundred kilohertz. These can be placed further from the supply pins and are clearly not required in the case of a battery-operated device.

The crystal should be placed as close to the RF IC as possible to ensure that via parasitic capacitances are minimized and to reduce any frequency offsets. The case of the crystal should be connected to ground using multiple vias to avoid radiation from ungrounded parts as any metal left unconnected and floating may act as an unwanted radiator. Using an isolating ground metal between the crystal and VDD traces will avoid any detuning effects on the crystal caused by the supply and will equally avoid the leakage of crystal or clock signals, and their harmonics, to the supply lines.

Good ground connections are vital, and there are a number of recommendations related to this practice. Traces near the ground pins of capacitors should be thickened to improve the grounding effect of the thermal straps (provided for cooling) and to minimize the series parasitic inductances between the ground pour (where unused areas of a board are filled with copper that is grounded) and the ground pins. Additional vias placed close to the ground pins of capacitors and connected to the bottom or inner layer ground plane will further help to reduce these effects.

The exposed pad footprint for the paddle of the RF IC should use multiple vias to ensure good grounding as well as a good heat sink capability. In the layout shown in Figure 2, there are 25 vias for a 7 mm x 7 mm-sized IC package, each 0.25 mm in diameter. If possible, the paddle grounds should be connected to the top layer ground metal to further improve RF grounding. This may be accomplished with diagonal trace connections through the corners of the IC footprint. Signals, especially higher frequency harmonics, can sometimes be coupled between the ground connections of nearby filter capacitors. Problems can be avoided by connecting these capacitors to ground on opposite sides of the transmission line.

In the area of the matching network, it is recommended to ensure a separation of at least 0.5 mm between traces or pads and the adjacent ground pours. This will minimize any parasitic capacitance and reduce detuning effects. With a 4-layer PCB, the first inner layer beneath the top layer should be filled with a continuous ground metal under the RF IC and the matching network. This technique will ensure a good low impedance signal path to the RF IC’s ground and, by not placing any wiring in this region, any coupling effects with the matching network will be prevented. It is also recommended that the ground return path between the ground vias of the Tx/Rx matching network and the ground vias of the RF IC paddle should not be blocked in any way. The return currents should see a clear, unhindered pathway through the ground plane back to the RF IC.

Finally, regarding the RF section specifically, connections to distant RF components such as the on-board antenna or antenna connector should be made using 50 Ohm grounded coplanar transmission lines. This will reduce sensitivity to any variation in signal caused by the PCB and will also reduce unwanted radiation and coupling effects. Radiation can be further reduced by multiple ground vias near the coupler lines. The use of transmission lines can be seen in Figure 3.

Best practice layout design for the entire PCB

While, as a minimum, it is good practice to have a large continuous ground metallization around the area of the RF section of a PCB, better performance may be obtained by applying this technique to the entire PCB. To achieve a good RF ground, the RF voltage potentials should be equal across the entire ground area. This helps maintain proper VDD filtering and also provides a good ground plane for monopole-type antennas. Gaps should be filled with ground metal, and the resulting sections on the top and bottom layer should be connected with as many vias as possible.

To reduce harmonic radiation caused by fringing fields, multiple grounding vias should be deployed at the edges of any ground metal area, especially at the edge of the PCB and around supply traces, as shown in Figure 3. In a board design with more than two layers, all of the wires or traces should be placed in one of the inner layers, especially supply traces, and the entire top and bottom layers should contain as much continuous ground metallization as possible to reduce any radiation from these traces. It is also recommended to avoid placing supply traces close to the PCB edge.

[Figure 3 | Entire board layout showing transmission lines and PCB edge ground vias]


We all appreciate the benefits of wireless connectivity whether it’s between our consumer-tech gadgets and our smartphones, tablets and laptops, or in the wider realms of the ever-burgeoning Internet of Things. The fulfillment of this promise depends on connecting all sorts of “things” together and to the Internet, many of which need to communicate wirelessly over reasonable distances while operating for long periods before batteries must be replaced or recharged.

Achieving the promise of the IoT also demands reliable, cost-effective connectivity solutions based on wireless SoCs that are easily integrated into end-product designs. However, RF design has never been easy, and getting the best performance out of an RF circuit layout can be challenging. Using a wireless SoC supplier’s reference design can be a good approach, but sometimes this isn’t possible. It is always important to follow good RF design practices to ensure the goals of communication range and power consumption are met without incurring issues of unwanted interference and failing to meet regulatory standard requirements.

Krisztián Kovács is Senior Director of Applications Engineering at Silicon Labs. He is responsible for worldwide customer support and applications development of the wireless IoT products and manages Silicon Labs’ R&D site in Budapest.

Silicon Labs





Kriszti?n Kov?cs, Silicon Labs