New SMARC Design Guide Helps with High-Speed Signals, Long-Lifecycle Engineering

August 10, 2021

Blog

All embedded hardware standards have two primary goals: Eliminate the need to recreate fundamental enabling technologies that provide little differentiation in end products and create an ecosystem of vendors that keeps solution costs low and customer flexibility high.

However, just because a solution is based on a standard doesn’t mean that it’s necessarily easy to implement into one’s design. For example, computer-on-module (COM) standards like COM Express from PICMG and the Standardization Group for Embedded Technologies (SGET) Smart Mobility Architecture (SMARC) both offer off-the-shelf processor modules that can simply be plugged into a design. But what they plug into, an application-specific carrier board, must be specially designed to the requirements of the target system.

Here, retaining flexibility in the standards comes with the byproduct of re-introducing a level of design complexity. To offset that, organizations like PICMG, SGeT, and others offer “Design Guides” that provide blueprints for the more open-ended portions of their respective specifications. SGeT, for example, published a Design Guide for its recently released SMARC 2.1.1 specification in June.

Inside the Guide

The new Design Guide is dedicated to the design of carrier boards that host SMARC 2.1.1-compliant modules, and is necessary because the latest release adds upgraded interface capabilities such as Gigabit Ethernet over PCIe SerDes signaling and USB-C with full support for features like USB 3.2 Gen1 and DisplayPort Alt Mode over a single interface.

The Design Guide helps carrier board designers route these signals and other signals to and from the processor module while minimizing crosstalk and EMI. In addition to covering traditional embedded interfaces, there is a section on the new USB technology and its various features; a complete chapter on the aforementioned SerDes implementations and others; and another on powering modules, which has been updated from previous Design Guides to better explain the SMARC specification’s four separate power domains and the power-up/power-down process.

The Guide also includes comprehensive examples and engineering best practices, including how via stubs are influenced by high-speed signals, SPI and eSPI topology considerations, and how to implement the RESET_OUT signal.

Visit https://sget.org/wp-content/uploads/2021/05/SMARCmodule_DG_V211.pdf for a pdf of the full Design Guide.

Designing for the Future

Most importantly, the Design Guide demonstrates how new SMARC carriers can be designed to maintain compatibility with Arm- and x86-based SMARC processor modules, as well as backwards compatibility with previous SMARC specifications. This ensures that engineers working with SMARC can design the technology into long-lifecycle systems where hardware/software reuse and upgradability are required.

“Almost 95 percent of Arm-based COMs are not standardized, as they offer mostly silicon dedicated pinouts. Such module pinouts are not well defined and documented, highly proprietary without peer review, and constantly being modified.” explains Markus Mahl, Product Marketing Manager at Data Modul and contributor to the SMARC 2.1.1 release.

“This makes it nearly impossible for potential users to find a long-term, suitable way through this jungle – not to mention the impossibility to re-use or upgrade their designs with next-generation silicon, which is a major accelerator for OEM’s ROI,” he continues. “Customers will therefore welcome the SMARC 2.1.1 module specification and the associated Design Guide 2.1.1 as one of the best-defined, detailed, silicon independent, future proof open specifications on the market.”

For more information, visit https://sget.org/standards/smarc.