Khronos Releases SYCL 2020 Specification

By Tiera Oliver

Associate Editor

Embedded Computing Design

February 16, 2021


Khronos Releases SYCL 2020 Specification

Update includes new features and closer alignment with ISO C++, SYCL adoption in embedded, desktop, and HPC markets

The Khronos Group announced the ratification and public release of the SYCL 2020 final specification, the open standard for single source C++ parallel programming. A milestone encompassing years of specification development, SYCL 2020 builds on the functionality of SYCL 1.2.1 to provide improved programmability, smaller code size, and increased performance. Based on C++17, SYCL 2020 enables ideal acceleration of standard C++ applications and drives a closer alignment with the ISO C++ roadmap.

First introduced in 2014, SYCL is a C++ based heterogeneous parallel programming framework for accelerating High Performance Computing (HPC), machine learning, embedded computing, and compute-intensive desktop applications on a range of processor architectures, including CPUs, GPUs, FPGAs, and tensor accelerators. SYCL 2020 will further accelerate adoption and deployment of SYCL across multiple platforms, including the use of diverse acceleration API backends in addition to OpenCL.

SYCL 2020 integrates more than 40 new features including updates for streamlined coding and smaller code size. Some key additions include:

  • Unified Shared Memory (USM) enables code with pointers to work naturally without buffers or accessors;
  • Parallel reductions add a built-in reduction operation to avoid boilerplate code and achieve maximum performance on hardware with built-in reduction operation acceleration;
  • Work group and subgroup algorithms add efficient parallel operations between work items;
  • Class template argument deduction (CTAD) and template deduction guides for suitable class template instantiation;
  • Simplified use of Accessors with a built-in reduction operation reduces boilerplate code and streamlines the use of C++ software design patterns;
  • Expanded interoperability enables efficient acceleration by diverse backend acceleration APIs;
  • SYCL atomic operations are now more closely aligned to standard C++ atomics to enhance parallel programming freedom.

More information can be found in the SYCL FAQ posted on the Khronos Blog.

In parallel with the release of the SYCL 2020 specification, the SYCL ecosystem continues to grow with the development of compilers, runtimes, libraries, and tools. Per the company, Intel’s oneAPI Data Parallel C++ (DPC++) already incorporates many SYCL 2020 features. Codeplay’s ComputeCpp SYCL 1.2.1 conformant implementation includes selected SYCL 2020 features as extensions, including support for DSPs and RISC-V with more features being added over time. The Intel and Codeplay implementations are based on the LLVM open-source compiler framework. hipSYCL from Heidelberg University also supports key SYCL 2020 features starting from version 0.9. Developers can download many of these implementations and experiment with SYCL 2020 features today.

At the Argonne National Laboratory, SYCL enables developers to easily scale C++ applications to use accelerator clusters in exascale supercomputer systems. According to the company, in Europe, the Cineca Supercomputing center is using the Celerity distributed runtime system, built on top of SYCL, to program the new Marconi100 cluster that is ranked #11 in the Top500 (Nov 2020).

The SYCL Working Group encourages users and tool implementers to download and explore the new specification Feedback on the SYCL standard is always welcome, including requests for future features. Feedback can be provided by visiting the Khronos SYCL Community Forum, the SYCL tech site, or Khronos Slack Channel

IWOCL & SYCLcon 2021, chaired by SYCL Working Group Chair, Michael Wong and sponsored by Khronos, takes place online on April 27-29. It will include an online SYCL tutorial covering the new SYCL 2020 features, as well as a dedicated SYCL panel discussion.

Registration is now open at

Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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