Enhancing Debug and Trace Capabilities for System Developers

By Enrico Carrieri

Principal Engineer - Intel

Mipi Debug Working Group

November 25, 2019


The systems are getting smaller and smaller and more and more complex, with a lot of different functionality being combined on a single chip.

Recent technological developments have resulted in a quantum leap in the complexity of system debug and optimization. The systems are getting smaller and smaller and more and more complex, with a lot of different functionality being combined on a single chip. There is more communication among multiple chips. Even what constitutes a bug has become more complicated to define.

Larger, more complex systems mean a longer, more arduous process of debugging, troubleshooting or fine-tuning devices. If it takes months for an organization to debug, that could amount to months of lost revenue.

Few want to pay extra for debug. It's kind of a necessary evil. Anything that can be done to minimize the impact of debug is valuable. MIPI Alliance’s broad portfolio of standardized debug and trace specifications are intended to streamline development for mobile systems in the Internet of Things (IoT), automotive, 5G, and other application areas.

Layered, Systematic Approach

MIPI has taken a layered approach to debug and trace, from the lowest level of the hardware, all the way up to the software layer. The idea is for an organization to be able to pick and choose the specifications it needs, strategically pop them into its development environment, then put its own value-add around the standard-layered set of interfaces and protocols. The portfolio of nine MIPI debug and trace specifications were recently made publicly available for download:

  • MIPI Gigabit Debug for IP Sockets (MIPI GbD IPS) v1.0—MIPI GbD IPS is an adapter for facilitating remote debugging of all types of connected devices, from smartphones to end points on the IoT.
  • MIPI Gigabit Debug for USB (MIPI GbD USB) v1.1—MIPI GbD USB minimizes debug’s impact on system functions and enables engineers to use USB connections to debug a device while the connection is carrying other traffic.
  • MIPI High-Speed Trace Interface (MIPI HTI) v1.0—MIPI HTI is a serial implementation of the data port, leveraging available high-speed serial interface technology by reusing the low-level physical high-speed portions of those interfaces in a bare-metal environment. In this way, MIPI HTI provides higher transmit bandwidth with fewer I/O pins compared with a parallel implementation.
  • MIPI Narrow Interface for Debug and Test (MIPI NIDnT) v1.2—MIPI NIDnT standardizes the use of functional ports on a device for debug and test procedures. The specification is intended to make it easier for developers to identify problems in complex designs and reduce development costs by minimizing reliance on expensive, proprietary testing tools. Designers enjoy the versatility of performing debug and test over other interfaces widely used in mobile and mobile-influenced designs.
  • MIPI Parallel Trace Interface (MIPI PTI) v2.0— MIPI PTI is a parallel interface with multiple data signals and a clock for exporting trace data about system functionality and behavior to a host system for analysis and display.
  • MIPI SneakPeek Protocol (MIPI SPP) v2.0—MIPI SPP allows for communication between a debug test system (DTS) and a mobile terminal target system (TS), facilitating software within the DTS to debug TS operation. Users reduce reliance on dedicated debug communication interfaces and take advantage of a familiar mechanism of address-mapped read and write transactions to observe, interrogate and adjust the TS.
  • MIPI System Trace Protocol (MIPI STP) v2.2—Developed as a generic base protocol that can be shared by multiple, application-specific trace protocols, MIPI STP allows its data streams to coexist with highly optimized protocols used to convey data about processor program flow, timing or low-level bus transactions.
  • MIPI System Software-Trace (MIPI SyS-T), v1.0—MIPI SyS-T is a common data format for transmitting software trace and debug information between a test system and a device, such as a system-on-chip (SoC) or platform. It provides a convenient approach—agnostic of vendor or operating system (OS)—to exchanging debug information across software, firmware or hardware implementations.
  • MIPI Trace Wrapper Protocol (MIPI TWP) v1.1—MIPI TWP enables multiple source trace streams to be collapsed into a single trace stream. Source byte streams are assigned system-unique identifications, and a wrapping protocol encapsulates all the streams in the system.

In addition, MIPI Debug for I3C, a specification for transporting debug controls and data between a DTS and TS, is in development and scheduled to be publicly available in 2020.

The MIPI Debug Working Group adhered to a number of different strategies in seeking to minimize the impact of the debug and trace processes. Reducing dedicated interfaces, for example, is especially important with regard to the IoT and other mobile application spaces where users cannot afford to devote prime real estate to extra pins and extra size. Having the ability to reuse interfaces and leverage functional interfaces addresses this need to efficiently use real estate, and so this requirement informs the working group’s development and refinement of the MIPI debug and trace specifications.

In addition, while developing the debug and trace specifications, MIPI sought to:

  • Minimize pin cost and boost performance of the basic debug interface
  • Increase bandwidth, capabilities and reliability of high-performance interfaces for exporting high-bandwidth, unidirectional processor trace data to debug tools
  • Deploy physically robust debug connectors with the performance required for high-bandwidth demands
  • Develop generic trace protocols allowing many different on-chip trace sources to be encapsulated onto a single trace data flow
  • Maximize debug visibility in fielded systems
  • Leverage mobile systems’ new high-bandwidth functional interfaces for debug transport

Freed to Focus on Value-add

By focusing on limiting the impact of the frameworks and protocols for moving data and providing control for debug and trace processes, MIPI has freed silicon providers and original equipment manufacturers (OEMs) to take maximum advantage of these standardized pipes and then invest in higher-value activities that help drive throughput.

For example, the specifications around trace; MIPI PTI, MIPI HTI, MIPI STP, MIPI TWP, and MIPI SyS-T, are particularly important relative to providing system designers and developers with visibility into the behavior of an embedded system.

A streaming interface on an embedded SoC can be used to export data about system functionality and behavior to a host system for analysis and display. Components monitoring processor instruction and data flow, instrumentation in the software running on a processor or components monitoring activities outside the processor, can provide data which allows developers to reconstruct or “trace” some aspect of system activity. The instruction execution sequence for one or more embedded processors, the data bus transactions made by an embedded processor core, the snapshots of transactions on system interconnects or streaming output from instrumented application code are examples of this trace data. The importance of this visibility is growing along with the complexity of embedded systems in mobile systems for the IoT, automotive, 5G, and other application areas.

By making the specifications publicly available, MIPI is enabling developers, tooling vendors and others to build value around the debug communication and trace data. In this way, it allows a strong ecosystem to take root, further broadening the specifications’ interoperability and enriching the development environment around them.

Debug strategist and architect focusing on platform solutions to enable hardware and software debug and trace across IoT, smartphone, tablet, Ultrabook, client, and server products. Also, working on industry standards on various debug technologies.

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