Menta S.A.S announced a technology IP cooperation with Andes Technology, a founding premier member of RISC-V International and supplier of 32/64bit RISC-V embedded CPU cores.

Andes is working with Menta to enable embedded programmable logic through eFPGA in its RISC-V AndesCore families. Menta and Andes share the same vision, providing customers with a joint solution that allows instruction set architecture (ISA) extension to be added or changed in the field.

Per the companies, extending RISC-V ISA with custom instruction set extension, based on eFPGA co-extended core, is the key differentiator for the next processor unit's generation. Designers will be able to add any instruction they need for the function that they want to accelerate, in the field. This is a feature that does not break any software compatibility and leaves space for development and differentiation.

The eFPGA plays the role of a hardware co-extended core for the RISC-V CPU, unlocking the possibility to add or reconfigure ISA for the duration of the product's life. Andes RISC-V processor families, already available in the SoC market as a mainstream computing engine, are now looking to enhance the product's ACE (Andes Custom Extension) feature by extending it with eFPGA hardware support.

ACE is a framework designed to define new instructions on the Andes RISC-V processor cores. By writing ACE scripts for instruction semantics and concise Verilog for instruction execution register-transfer level (RTL), SoC designers can use Andes COPILOT (Custom-OPtimized Instruction deveLOpment Tools) to generate all required components automatically and extend the existing Andes processor package, including the processor RTL, compilation tools, debugger and cycle-accurate simulator, to support the new instructions to accelerate domain specific applications.

"By cooperating with Menta, we enable a brand new usage of Andes CPU cores to the market that embraces the characteristic of extensibility for the RISC-V ecosystem, especially in applications that require space for development and differentiation including AI and 5G," said Chief Technology Officer and Executive Vice President of Andes Technology Dr. Charlie Su. "Customers can optimize and enrich their hardware with expected scale of cost by using Menta eFPGA solution to make reconfiguration of ACE custom instruction possible in post-silicon updates."

The delivery of Menta pre-programmed eFPGA cores combined with the Andes RISC-V CPU cores will be provided with specialized user interface tools to program the eFPGA matrix and set up the RISC-V application programmable parameters, within a complete and optimized software solution.

For more information, visit: https://www.menta-efpga.com/