RISC-V Summit, San Jose. MIPS has designated Imperas to deliver flexible framework RISC-V processor verification tools to simplistically adapt from issue recognition and debug resolution in a testbench ecosystem consistent with the SystemVerilog EDA tools. The provided tools support the open standard RVVI (RISC-V Verification Interface) with the ability to communicate with a processor.

RISC-V Summit, San Jose. Codasip announced its SecuRISC5 for reliable custom compute that utilizes reference designs merging Codasip IP and third-party technology. The recently launched Codasip Labs¹ will recognize openings where SecuRISC5 will be attentive, a hub, and a coordinator of pan-industry collaboration.

Intel and the RISC-V Foundation have collaborated on an initiative to further expedite the expansion of RISC-V architecture with the launch of the Intel® Pathfinder for RISC-V, a pre-silicon developer environment equipped with RISC-V cores, a set of IPs, and various operating systems and toolchains.

Codasip announced that quantum-resistant secure tools from Veridify Security Inc. are now available to support Codasip’s RISC-V processors with a secure-boot function.

Accelerating AI inference models has become an essential task as we progress towards creating more sophisticated and efficient AI applications. Flexibile and complete AI assistance are critical components for success in the fast-growing AI sector. 

On this episode of the Embedded Insiders, Brandon and Rich discuss the impact of Russia’s invasion of Ukraine on the electronics industry.

It's all about money! In this edition of the Embedded Insiders, Brandon and Rich break down some major acquisitions, like Arm's purchase of NVIDIA, as well as AMD potentially buying Xilinx.