MIPS and Imperas Collaborate on Verification Tools for RISC-V Processors

By Chad Cox

Production Editor

Embedded Computing Design

December 13, 2022


Image Provided by MIPS and Imperas.

RISC-V Summit, San Jose. MIPS has designated Imperas to deliver flexible framework RISC-V processor verification tools to simplistically adapt from issue recognition and debug resolution in a testbench ecosystem consistent with the SystemVerilog EDA tools. The provided tools support the open standard RVVI (RISC-V Verification Interface) with the ability to communicate with a processor.

“At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors,” said Don Smith, Vice President Engineering at MIPS. For superscalar performance with multi-issue Out-of-Order (OoO) execution and multi-threading, MIPS released its eVocore P8700. The P8700 has the capacity to scale to 64 clusters, 512 cores, and 1,024 harts/threads. Smith continues, “As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.”

MIPS has released its eVocore I8500 is scalable to  an in-order multiprocessing platform linking multi-threading and a triple issue pipeline. and can scale to 64 clusters, 512 cores, and 2,048 harts/threads.

“Since 2010, MIPS core IP deliverables have included the Imperas based ISS, and as a consequence our technology has helped to support many projects in applications such as high-performance wireless communications, networking, automotive and AI applications,” said Simon Davidmann, CEO at Imperas Software Ltd. “With MIPS’ strategic shift to RISC-V, we are pleased to continue our long-standing relationship with new technology and innovation for verification for the latest MIPS RISC-V based Applications-Class processors.”  

For more imformation, visit Imperas.com/ImperasDV.

The RVVI (RISC-V Verification Interface) specification is available for download here.  

*RISC-V Summit 2022 Imperas is proud to be a contributing Diamond sponsor for the fifth annual RISC-V Summit, December 12-15, 2022, in San Jose, California. Imperas will showcase solutions for RISC-V processor verification, custom instruction design flows, and software development, including a keynote on RISC-V Processor verification plus many other activities. For more information, please visit RISC-V Summit 2022.

Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.

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