EMA Design Automation Expands Operations in Central Europe

Taryn Engmark

January 12, 2022

Simplifying Design Verification for Increasingly Custom RISC-V Processors

Brandon Lewis , Saumitra Jagdale

December 10, 2021

SiFive Essential 6-Series, 21G3 Release Add Mid-Range Performance & Features to Leading RISC-V IP Portfolio

Brandon Lewis

December 10, 2021

Siemens Extends Support of Multiple IC Design Solutions for Samsung Foundry’s Latest Process Technologies

Tiera Oliver

November 29, 2021

Real-time Ray Tracing Technology: A Game-Changer for Mobile Graphics

Kristof Beets

November 17, 2021

“Total Solutions for IoT” Virtual Dev Platform Cuts Lifecycles by up to Two Years

Taryn Engmark

October 21, 2021

Embedded Executive: Jeff DiCorpo, SVP Business Development, efabless

Rich Nass

July 7, 2021

Power Modeling and Estimation in Early System Design, Part 1

Deepak Shankar

June 28, 2021

Product of the Week: Cadence Spectre FX FastSPICE Simulator

Embedded Computing Design Staff

June 22, 2021

IBM's 2 nm Transistor Breakthrough Puts Chip Design Under the Microscope

Anupurba Mukherjee

June 18, 2021

Sondrel Reference IP Enables HPC SoCs While Reducing Cost and Design Time by 30 Percent

Brandon Lewis

May 18, 2021

Sondrel has added the SFA 300 reference design to its semi-custom SoC IP portfolio. Consisting of four-CPU clusters featuring 4 TOPS per channel of AI processing and 400 GOPS per channel of DSP performance, clusters can be daisy chained via the PCIe interface to create HPC solutions. The IP reuse solution enables the creation of differentiated AI, 8K video, blockchain, data analytics, and other high-performance data processing solutions by integrating customer-specific IP such that design time and cost can be reduced by up to 30 percent.

SmartDV Automation Tool Suite Accelerates Protocol Debug, Testbench Creation

Brandon Lewis

May 17, 2021

SmartDV has packaged the SmartViP Debug, a tool designed for automated protocol debugging, and SmartTestBench, which automatically generates testbench files and includes a variety of verification scenarios, into a unified automation tool suite. By identifying protocol violations and presenting them in graphical views or through tabular or text-based representations, the combined offering helps eliminate manual verification processes.

Sigasi Studio Offers Free Coding & Syntax Tools for Digital Designers

Brandon Lewis

May 15, 2021

TSMC Certifies Aprisa Place-And-Route Solution from Siemens on TSMC‘s N6 process

Tiera Oliver

April 22, 2021

Sondrel Invests Heavily in Own R&D Program

Sondrel

March 29, 2021

ADLINK Launches the DLAP x86 Series, a Deep Learning Acceleration Platform for Smarter AI Inferencing at the Edge

Tiera Oliver

February 2, 2021

AI Compilers and the Race to the Bottom

Brandon Lewis

November 5, 2020

Making the Switch to Macintosh as an Engineer

Jeremy S. Cook

November 3, 2020

Potential Design Cost Savings from Using AI Tools for SoC Designs Ranges from 20% to 30%, says Semico Research

Tiera Oliver

October 27, 2020

Reduce DFT Footprints in ASIC Design by Addressing Test Time

eInfochips

October 22, 2020

DEV KIT WEEKLY: Lattice Semiconductor CrossLink-NX Evaluation Board

Brandon Lewis

October 16, 2020