Preserve Data Center Power with 3 nm PCIe 6.0 Switches

May 19, 2026

Blog

Data centers are being constructed more rapidly as the trend of increasing data generation continues, and data must be stored and transferred. Increased use of artificial intelligence (AI) and machine learning (ML) are among the many applications boosting their reliance on data access.

Transferring substantial amounts of data for processing by high-performance computing (HPC) clusters requires considerable computing resources with high-speed, wide-bandwidth switched signal paths to share data efficiently and effectively. The hundreds and thousands of servers, GPUs, SoCs, FPGAs, and CPUs at work in a typical data center require enormous amounts of electrical energy for operation, and the amount of power required will only increase as data centers grow and expand their capacity. Those data centers are the foundations of the modern computing “cloud” data storage, enabling easy access to AI and ML for users across a wide range of markets.

Fortunately, high-speed switching enables reliable routing of data through many lanes of signal traffic in a data center. A variety of switch formats contribute to data routing, with formats such as Peripheral Component Interconnect Express or PCI Express® (PCIe®) providing the ease of installation and interconnection of a well-adopted industry standard. PCIe connectors are commonly used inside computers and servers to link high-speed components, and the standard has progressed to its sixth generation, PCIe Gen 6 (PCIe 6.0), with wider bandwidth and faster switching speed over the previous PCIe 5.0 generation.

In addition, because of the looming power consumption of expanding data centers, PCIe 6.0 transfers greater amounts of data than the previous five versions and saves on power consumption. For example, the latest PCIe 6.0 fanout switches from Microchip Technology (www.microchip.com) control as many as 160 lanes of bidirectional data transfers with their wide bandwidths and fast switching speeds. They achieve high performance via a 3 nm silicon (Si) semiconductor fabrication process that realizes high circuit density and excellent power efficiency, characteristics required by components needed to handle the growing volumes of modern data centers.

PCIe connectors are widely used in desktop personal computers, servers, automated industrial systems, and entertainment systems. They are known as “edge-board” connectors because of their position on a circuit board. They are characterized by mechanical parameters, including pitch, and electrical performance specifications, such as how many billions of transfers they can execute per second (GT/s or Gtransfers/s). PCIe standards have increased transfer rates with each generation, with the first generation (PCIe 1.0) supporting 2.5 GT/s, the second generation doubling the speed to 5 GT/s, the third generation increasing it to 8 GT/s, the fourth generation doubling that speed to 16 GT/s, the fifth generation moving up to 32 GT/s, and the current generation, PCIe 6.0, extending the switching speed to 64 GT/s.

Transferring data within and between data centers requires sufficient operating power along with the software and hardware to execute data transfers quickly and efficiently. Because substantial amounts of power are needed to operate data centers, and heat is generated as a byproduct of the power consumed, many data servers employ liquid cooling in their servers. Some data centers have even adopted heat-reuse practices and recycle the excess heat for sale to neighboring communities.

High-speed PCIe switches, which are key components within the cloud and its data signal paths, were developed as a means of standardizing configurations such as fanout switches for ease of installation in multiple applications. Each PCIe generation increases the performance and capabilities requirements of the standard to better serve the increasingly difficult challenges faced by larger and faster data centers to handle growing amounts of data.

The PCIe 5.0 standard, established in 2019, set impressive performance levels, with excellent guidelines for efficiently transferring large volumes of data. But with rapidly growing demands for increasing data from AI and ML applications, the PCIe 6.0 standard is an inevitable next step in defining switching solutions for high-speed, high-volume data communications. The PCIe 6.0 standard features a bandwidth of 32 GB/s per lane or 256 GB/s total bandwidth for a 16-lane setup or double the capacity of a PCIe 5.0 switching configuration. PCIe 6.0’s data transfer rate of 64 Gtransfers/s per lane is twice that of PCIe 5.0.

While PCIe 5.0 uses non-return-to-zero (NRZ) encoding and no error correction, PCIe 6.0 employs four-level, pulse-amplitude-modulation (PAM4) encoding and advanced error correction. The newer standard features forward error correction (FEC) and cyclic redundancy check (CRC) to assist in handling the much higher data density and higher bit error rates (BERs)  associated with PAM4 signaling. Both PCIe 5.0 and 6.0 are backward compatible with earlier PCIe 1.0, 2.0, 3.0, and 4.0 versions.

PCIe 6.0 Formula

PCIe 6.0 fanout switches provide performance and capabilities according to sixth-generation PCIe specifications. They fan out by splitting a single high-speed, wide-bandwidth port into numerous lower-bandwidth output connections. For example, a server might use a fanout switch to divide a high-speed 100-Gb/s uplink port into four 25-Gb/s or eight 12.5-Gb/s links. Switches capable of port bifurcation achieve it at a specified multiplication ratio, such as ×4, ×8, or ×16. Fanout switches with PCIe connectors transfer data over a given number of lanes, with the lanes serving as data signal paths between a controller and connected devices. Switches with the highest number of lanes can handle the highest amounts of data.

The latest generation of these PCIe 6.0 switches, as embodied by the Switchtec™ PCIe 6.0 fanout switches from Microchip, must be fabricated with the highest circuit density possible to support large numbers of lanes within a small switch package size. Si semiconductor foundries fabricated wafers with a 3 nm process can realize the microscopic circuit dimensions needed for PCIe 6.0 switches. Fabricated with a 3 nm Si foundry, PCIe 6.0 switches achieve 15% to 20% improvement in power efficiency over previous-generation PCIe 5.0 switches. The 3 nm PCIe 6.0 switches, and the expertise that led to their development, accelerate data transfers at data centers even as they help trim power consumption and cut operating costs in the face of growing AI and ML data handling requirements. The PCIe Gen 6 connectors on the fanout switches are backwards compatible and physically footprint interchangeable with earlier generations.

Fig. 1 Microchip’s Switchtec PFX/PSX PCIe 6.0 fanout switches provide as many as 160 lanes, 20 ports, and 10 stacks per switch

PCIe 6.0 fanout switches in Microchip’s Switchtec PFX and PSX lines are designed to handle as many as 160 lanes, 20 ports, and 10 stacks per switch (Fig. 1, picture of a switch). They provide scalable, power-efficient data-transfer solutions for data connectivity infrastructure where power consumption is a concern, such as AI and enterprise data centers. They perform port bifurcation at factors of ×8 and ×16 to serve a wide range of applications. The switches are designed to maintain high signal integrity (SI), using software-controlled Active State Power Management (ASPM) to conserve power consumption and Advanced Error Reporting (AER) on all ports to minimize errors. The switches integrate MIPS microprocessors to assist with configuration and support a variety of input/output (I/O) interfaces.

The 3 nm Si semiconductor process with which the Switchtec fanout switches are fabricated is representative of a trend in the densification of semiconductor devices, where transistors are being brought closer together to fabricate more functionality within smaller device sizes at lower power levels. The length of 3 nm is not the actual device channel length or any dimension of a semiconductor device, but serves to differentiate the semiconductor process from earlier processes, such as 5 nm, with larger device dimensions and spacings. The 3.0-nm process enables fabrication of shorter gate lengths and denser integrated circuit (IC) layouts compared to an earlier 5-nm process. A 3 nm process enables “die shrinking” to create ICs with increased density while also reducing power requirements to help shave power consumption of a fabricated device (Fig. 2).

Fig 2: Microchip CEO Steve Sanghi holds one of the 3 nm wafers. The PCIe 6.0 fanout switches are fabricated with a 3 nm process to achieve dense circuits with excellent power efficiency.

Switchtec Switches

Taking a closer look at Switchtec PFX/PSX Gen 6 Fanout PCIe switches, the model PM60160A supports as many as 160 lanes, while the model PM60144A PCIe 6.0 fanout switch provides as many as 144 lanes. Suitable for AI accelerators in data center equipment, the 160-lane PCIe 6.0 fanout switches support 20 ports and 10 stacks, while the 144-lane device supports 18 ports and 9 stacks. Each port can accept hot and surprise-plug features. The PCIe fanout switches (Fig. 3) feature advanced security, including a hardware root of trust and secure boot via post-quantum safe cryptography compliant with Commercial National Security Algorithm Suite (CNSA) 2.0.

The switches connect to passive, managed, and optical cables, and GPIOs can be configured for numerous cable/connector standards. For larger topologies, the switches can be employed with logical non-transparent bridging (NTB) interconnects. Models, PM60160A and PM60144A, work with flexible clocking architectures, with input and output reference clocks based on the configuration of the PCIe stack. As many as four input clocks can be used for each stack. In addition, Microchip has developed an extensive collection of clock and timing solutions for every PCIe application.

Fig 3: The Switchtec PFX/PSX PCIe 6.0 fanout switches support port bifurcation at ×8 and ×16. This example shows how the switches provide interconnections with multiple CPUs and GPUs at a bifurcation of ×16 in a typical data center application.

The switches perform nontransparent bridging (NTB) to simplify connections in multiple-host domains. They add forward error correction (FEC) in the form of Flow Control Unit (FLIT) mode as part of the PCIe 6.0 standard and provide simple, direct interfaces between GPUs in a server rack to help lower latency in the network. For error containment, the switches offer advanced error reporting (AER) on all ports, with downstream port containment (DPC) on all downstream ports. In addition, Completion Timeout Synthesis (CTS) helps prevent an error state in an upstream host due to incomplete, non-posted transactions.

The Switchtec Gen 6 PCIe switch family is supported by Microchip’s ChipLink® diagnostic tools, which provide debug, diagnostics, configuration, and analysis through an intuitive graphical user interface (GUI). ChipLink tools perform analysis using in-band PCIe or sideband interfaces such as UART, TWI, and EJTAG, enabling flexible and efficient monitoring and troubleshooting during the design and development of products that incorporate these fanout switches, including AI accelerators and other data center components. In addition, the switches can be evaluated using the PM61160-KIT Switchtec Gen 6 PCIe Evaluation Kit (Fig. 4). This latest-generation evaluation kit builds on those available for earlier PCIe switch families and supports multiple interfaces for ease of use.

Fig 4: The PM61160-KIT Switchtec Gen 6 PCIe Evaluation Kit enables developers to explore a wide range of applications for Switchtec PCIe 6.0 fanout switches.

PCIe 6.0 switches are essential components in modern data centers, particularly when extremely high transfer speeds are required to move large volumes of data. When high efficiency is also critical for conserving power in large-scale data centers, the combination of advanced features offered by Microchip’s Switchtec PFX/PSX PCIe 6.0 fanout switches—along with their flexibility across multiple interfaces—makes them a clear choice for transferring substantial amounts of data in next-generation data center environments.

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Tam Do is an experienced technical marketing and application engineering leader with more than 30 years of experience in the semiconductor and systems industry. His background spans product lifecycle management, global customer engagement, and revenue growth across video, consumer mobile, IoT, and data center applications. Do holds a Bachelor of Science in Electrical Engineering from the University of Nevada, Reno, an MBA from the University of Phoenix, and is fluent in Chinese.