Ventana's Veyron V1 is a RISC-V Powerhouse
December 15, 2022
RISC-V Summit, San Jose. Ventana Micro Systems Inc.’s founder and CEO Balaji Baktha will present Ventana’s Veyron family at his RISC-V Summit keynote address. The standards based Veyron V1 is a RISC-V processor that will come in chiplets and IP assisting in single thread performance targeting solutions for data centers, automotive, 5G, AI, and client applications.
"Our vision of delivering the highest performance RISC-V CPUs is helping to reshape next generation high performance open hardware architectures," said Balaji Baktha. The Veyron V1 leverages RISC-V’s open architecture and extends Moore’s Law for data centers that are limited by energy and thermal restrictions.
Included with Ventana’s Veyron V1 is a Software Development Kit (SDK) containing a comprehensive set of software building blocks established on Ventana's RISC-V platform.
Highlights of the Veyron V1 are:
- Eight wide, aggressive out-of-order pipeline
- 5nm process technology
- 16 cores per cluster
- High core count multi-cluster scalability up to 128 cores
- 48MB of shared L3 cache per cluster
- Advanced side channel attack mitigations
- Comprehensive RAS features
- Top-down performance tuning methodology
- Provided with IOMMU and Advanced Interrupt Architecture (AIA) system IP
- SDK released with necessary software already ported to Veyron
- Veyron V1 Development Platform available
Baktha continues, "Today, we have a significant first mover advantage by providing a platform that can allow customers to innovate and differentiate. Markets which require high performance compute such as Data Center, 5G, AI, Automotive, and Client will all benefit from our open standards-based, ultra low latency chiplet solution that delivers rapid productization with significant reduction in development time and cost compared to the prevailing IP models. Ventana's strong roadmap and customer engagement puts the company in prime position for sustained market leadership."