Long live power management!

September 10, 2015

Long live power management!

The 52nd Annual Design Automation Conference (DAC52) at San Francisco's Moscone Center had a number of interesting power-management announcements, mak...

The 52nd Annual Design Automation Conference (DAC52) at San Francisco’s Moscone Center had a number of interesting power-management announcements, making this one of the hottest topics of the show. Having immersed myself in a full week of low-power issues, I thought it appropriate to consider how the industry sees the challenges of low power and the different approaches being adopted.

Before we look to the future, consider why power management is now the most critical issue for portable products. To paraphrase Bill Clinton, “It’s battery life, stupid.” With the advent of the Internet of Things (IoT) and the emergence of wearable technology, power consumption and battery life have become paramount. As healthcare-related IoT devices become a reality alongside lifestyle wearables specifically designed for health monitoring, the problem will become more acute.

The traditional approach to power reduction uses variants of operating voltage scaling to reduce power. But this can no longer deliver the necessary improvements, forcing a move toward selective powering-down of functional blocks, which limits both device usability and flexibility. The traditional sleep mode seen in laptop computers may enable faster boot-up, but usability in this mode is almost non-existent: A new, more intelligent mode of power management is clearly needed – and demanded.

Power is The new king

Battery-powered devices, particularly for long-life applications, demand a power management approach that delivers greater intelligence, flexibility, and, most importantly, a longer battery life. Many vendors at DAC52 were promoting power management as a key issue, but few were willing to venture how new power management regimes would operate.

The challenge is coming from two different factions in our always-connected world. As more features are integrated onto a single system-on-ship (SoC), the amount of integrated memory also increases. By 2017, integrated memory, much of it SRAM, will consume more than 70 percent of an SoC’s active area – and a similar amount of power if not carefully managed. The new generation of smart watches, led by Apple, have a recharging cycle measured in hours, some as low as 18 hours. It’s clear that future wearables must deliver user functionality measured in days and weeks, not hours.

New regime for power management

Here’s a bold prediction: The hot topics at DAC53 and 54 will be effective and accurate power prediction and management tools. EDA vendors will promote advanced analysis capabilities that can accurately estimate power across a complex set of operating conditions. Devices will feature variable power consumption depending on the application demands; integrated self-learning power management algorithms will become commonplace.

Why? Because today’s power consumption controls are based around full, reduced, or stand-by power, are selectable via software or hardware, and offer insufficient granularity and flexibility. Emerging power management strategies, on the other hand, will incorporate automatic system-level power reduction schemes that deliver just enough power to deliver application functionality, whatever that may be.

Employing embedded SRAM is one way to address that scheme. Within embedded SRAM, adjustable back bias, full speed, retention mode, and deep sleep power savings address some of the rudimentary elements of analog power management. By 2017, many of the leading EDA vendors will incorporate multiple-modal power consumption analyses into their mainstream tools. Power adjustment will be thought of as a continuum from the lowest level of hibernation to full-on high performance operation.

Dr. Duncan Bremner, CTO of SureCore Ltd., has 30 years of experience in the semiconductor industry, predominantly in new product development. He spent 17 years at National Semiconductor in telecom product development, becoming the company’s youngest Member of Technical Staff before leaving to establish Intel’s high-speed development center for communication products. Duncan is the cited as the inventor on more than 15 patents and has overseen 40 patent filings on his projects.

Dr. Duncan Bremner, SureCore Ltd.
Analog & Power