IEEE 1149.7: Expanding and improving JTAG
November 01, 2008
Rather than replacing the IEEE 1149.1 standard, IEEE 1149.7 expands its functionality and provides new scan topologies.
The IEEE 1149.1 standard was adopted in 1990. Built upon the work of the Joint Test Action Group (JTAG), it provided a pins-out view from one IC pad to another to help test engineers locate and discover faulty PC boards. A description of the boundary scan description language was added in 1994.
Complications arose as chips increased functionality and designs shifted away from PC boards to multichip modules and stacked die packages. These difficulties included handling the pin count requirements and multiple Test Access Port (TAP) controllers for System-on-Chip (SoC) devices, testing multichip modules and stacked die configurations, enhancing debug performance, and improving test and debug logic power-down in low-power conditions.
Organizations like the Mobile Industry Processor Interface Alliance and the NEXUS 5001 Forum took up the challenge to solve the problems specific to their industries. Their work laid the foundation for the IEEE 1149.7 standard, which is expected to be ratified early next year.
Increasing test system functionality
Rather than replacing IEEE 1149.1, the new IEEE 1149.7 standard expands its functionality by reducing the number of pins used. This provides new scan topologies that are favorable to stacked die and multichip module configurations and offers advanced capabilities to aid in software debug.
IEEE 1149.7 goals
- Be compatible with existing IEEE 1149.1 systems
- Operate with fewer pins
- Provide background instrumentation capability using the same pins
- Provide mechanisms for TAP power management
- Preserve gateway for debugging semiconductor errors/defects
- Improve performance for selected debug use cases
- Preserve investment of semiconductor IP, software IP, and existing debug and test tools
- Provide a framework for other debug pin protocols to gain access to the pins
The IEEE 1149.7 standard has two groups of capabilities: Classes T0 through T3, which extend IEEE 1149.1 and enable new operations, and Classes T4 and T5, which are focused on advanced two-pin operation.
Class T0 ensures compliance with the industry‚Äôs test infrastructure by setting up IEEE 1149.7 devices to make them act compatibly with IEEE 1149.1. These techniques include the use of N-bit IR, 1-bit DR for bypass instruction, mandatory IDCODE (32-bit path), and mandatory instructions behaving as specified in the IEEE 1149.1 specification. After a test logic reset is initiated, all multi-TAP devices must conform to the mandatory IEEE 1149.1 instruction behavior and implement a 1-bit DR scan for the bypass instruction.
Class T1 instantiates a control system for the IEEE 1149.7 standard that is transparent to IEEE 1149.1 devices, providing a foundation for the advanced functionality implemented in Classes T1 through T5 without changing the IEEE 1149.1 state machine. In addition to creating a control system, this class addresses the needs of power-sensitive devices with four power-down modes.
The key innovation is the combination of the IEEE 1149.1-compatible TAP state sequences and shift state watching, which creates an IEEE 1149.7 control system that utilizes the bypass or IDCODE instructions plus a series of IEEE 1149.1-compliant sequences called Zero-Bit DR Scans (ZBS), shown in Figure 1.
Beginning at zero, the ZBS count is incremented with each consecutive occurrence of a ZBS without encountering a Shift-DR TAP Controller (TAPC) state. When a DR scan containing a Shift-DR occurs and the ZBS count is greater than zero, the ZBS count is locked, activating a corresponding control level (shown in Table 1).
Commands are typically 10-bit values and consist of two consecutive DR scans while the controller is locked at Control Level 2. Command Part 1 (CP1) provides a 5-bit operating code, and Command Part 2 (CP2) provides the immediate operand, which is the lower 5 bits of the command. The function specified by the command is performed when CP2 completes.
A three-part command can be created by appending a third DR scan (a Control Register or CR scan) after CP1 and CP2 and transporting a data value. Each of the three three-part commands has a special purpose.
To achieve higher performance for engineers involved in testing high chip count applications, Class T2 offers a chip-level bypass mechanism that shortens scan chains and another mechanism that provides hot connect capability. Class T2 adds three scan formats to implement these new features:
- JSCAN0: Offers IEEE 1149.1- compliant operation.
- JSCAN1: Provides hot connection and disconnection protection. At power-up, bypass can be the default (JSCAN1 format). This protects TAPs from spurious signals and prevents core corruption during hot connections.
- JSCAN2: Implements bypass to improve series connected devices‚Äô performance. The mechanism also functions as a firewall, enabling access to chip TAPs only after a predetermined sequence is initiated. This security measure ensures that only a debug test controller can access the system once a running, powered target has a stable electrical connection.
Although provisions for boundary scan testing using a star topology are included, IEEE 1149.1 does not provide enough detail to make this mode of testing viable. A new scan format ‚Äì JSCAN3 ‚Äì is included in IEEE 1149.7 to correct this omission. A write-only register used to specify the scan format and a device address assignment for star configurations also have been added to the new standard.
IEEE 1149.7 supports both series and star topologies, the latter of which is preferable for testing stacked die configurations. Star topology is desirable for stacked die configurations because the location of the debug connection is consistent. Whereas Figure 2a shows the series scan topology, Figure 2b illustrates the Star-4 or Wide Star configuration.
IEEE 1149.7 maintains compatibility with the IEEE 1149.1 standard by making all operations appear to be series scans using Capture-xR and Update-zR TAPC states in a group of selected IEEE 1149.7-enabled TAP controllers. To operate in this mode, chips in the star configuration must be assigned Controller Identification (CID) numbers. An iterative arbitration system is used to assign CIDs, and operations are executed using Control Level 2.
To address the rising number of pins in SoC devices, Class T4 adds scan formats to support transactions with two pins instead of four, resulting in fewer total pins required on chip packages. This also helps with stacked die configurations because it is highly desirable to have the fewest number of connectors possible when die are stacked.
The key to two-pin operation is eliminating the original data lines and sending bidirectional serialized data over the Test Mode Select (TMS) line, which is renamed TMS Counter (TMSC). To implement this capability, the glueless star config-uration from Class T3 is utilized, this time without Test Data In (TDI) and Test Data Out (TDO). This is the Star-2 configuration shown in Figure 3.
Besides reducing pin count, Class T4 defines optimized download-specific scan modes in which only useful information is downloaded. To improve pin operation performance, the clock rate also can be doubled. These features combined with the optimized transactions do not cause performance loss, instead improving performance in some cases.
Class T5 functionality is beneficial primarily to software designers utilizing JTAG for debugging. This class gives the test port the ability to perform debug and instrumentation operations concurrently (data is transferred during idle time), which reduces the number of pins dedicated to instrumentation, and enables custom protocols to use the pins, a feature many vendors offer in nonstandard ways. Class T5 standardizes the process to access the pins.