PGY-LA-EMBD All-in-One Oscilloscope, Logic, and Protocol Analyzer for Embedded Interfaces

By Saumitra Jagdale

Freelance Technology Writer

June 18, 2021


PGY-LA-EMBD All-in-One Oscilloscope, Logic, and Protocol Analyzer for Embedded Interfaces

Testing and debugging has always been a tedious phase for engineers in the hardware design life cycle. Finding the issues and backtracking errors consumes a lot of productive time which causes the delay in production. Hence, the concept of capturing and monitoring the electronic signals using a Logic Analyzer solves this issue for a Test Engineer to analyze the hardware design.

Prodigy Technovations’ Discovery Logic Analyzer series allows design engineers to debug timing problems and perform simultaneous protocol analysis. This simultaneous analysis saves a lot of time in the protocol debugging process. The device comes with the support of I2C, SPI, and UART protocol analysis. Further, it is a PC-based device for debugging and testing embedded systems for hobbyists, small engineering teams, and startup enthusiasts.

The device comes with ten logic channels for monitoring the signals. The voltage range for the logic levels of the device is around 1.2-5V. The host connectivity is through a USB 3.0 Type C port for the logic analyzer. It has a wide range of triggering options for debugging which include auto, pattern, delay, and pulse width trigger. 

Signal Capturing in PGY-LA-EMBD

The Discovery Logic Analyzer features two options for signal capturing. These include synchronous and asynchronous analysis in terms of the clock. The synchronous capture is a state analysis that verifies the signals corresponding to the system clock in reference to the given design parameters. Whereas asynchronous capture is a timing analysis that checks the signals with respect to clock signals at varying sample rates.

Synchronous State Analysis View

The synchronous state analysis view allows designers to monitor the signal behaviour with respect to timestamps. The system clock is the reference for plotting data signals with the bus diagram. Hence, it gives the option of grouping the signals so that design engineers can view multiple signals at a time. The time correlation of the signals in the state analysis view helps design engineers optimize the code in terms of design.

Asynchronous Timing Analysis View

The asynchronous timing analysis is one of the interesting features of the Logic Analyzer. The device gives an option for selecting the sampling rates as per the analysis requirement of the designers. This allows the investigation of the glitches, which are the main cause for the bugs in a hardware design. The timing analysis view also has a grouping functionality for monitoring multiple signals at a time. The interface has a marking and zooming feature for debugging the timing errors in the waveforms, which also allows the analysis of the captured data at any point for a long capture duration.

The PGY-LA-EMBD Logic Analyzer features the functionalities of the following devices. This allows the design debugging and validation.

  1. Oscilloscope: For displaying and analyzing real-time electronic waveforms
  2. Logic Analyzer: For monitoring the displaying the signals on multiple channels
  3. Protocol Analyzer: For analyzing the protocol signals and data traffic over communication channels.


Oscilloscope+Logic Analyzer+Protocol Analyzer

The Solution to Design Debugging Problems

One of the major challenges for design engineers is the multiple interface testing of the hardware. The logic analyzer solves this challenge by providing multiple interface support including the SPI, UART, and I2C protocols. Also, the PGY-LA-EMBD enables simultaneous logic and timing insights of different points of the circuit. This reduces the time for debugging in case of mismatch signal parameters. 

Hands-on Use Case

The protocol decode view of the device provides packet information in each state and packet details along with error information. Additionally, the device comes with the option for selecting the frame in the protocol list which auto correlates with the timing view. This can provide information on protocol errors and design engineers can take actions accordingly.

Protocol Decode View

The device works at a timing speed of 1GS/s on all channels, thus the precision of time analysis is in order of 1ns. This enables the engineers to monitor the glitches even in a 1ns timestamp, which is one of the most precise methods for design debugging. The logic analyzer comes with the option of long duration capture, hence making it suitable for predictive and maintenance analysis. The reports can also be generated in the PDF and CSV format for documentation purposes.

If your hardware design requires some more logical channels and protocol support. You can also go for a 16 channel logic analyzer from Prodigy Technovations, compatible with I3C, SPMI, and RFFE protocols as well. Both the models of the PGY-LA-EMBD logic analyzer have the same form factor with a lightweight of 200 gms.

For more information regarding the software support and technical specifications, you can visit the official datasheet of PGY-LA-EMBD.

The 10 channel LA is available at $1000 USD and 16 channel LA is available at $1500 USD on the product page.

Saumitra Jagdale is a Backend Developer, Freelance Technical Author, Global AI Ambassador (SwissCognitive), Open-source Contributor in Python projects, Leader of Tensorflow Community India, and Passionate AI/ML Enthusiast.

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