Efinix Announces Availability of Three RISC-V SoCs
June 02, 2020
News
Efinix announced availability of a series of three software defined, SoCs based on the RISC-V core. The Ruby, Jade, and Opal SoCs.
Efinix announced availability of a series of three software defined, SoCs based on the RISC-V core, Ruby, Jade, and Opal.
The three designs have been optimized for Efinix's Trion family of FPGAs and provide compute and I/O capabilities in devices from the T8 to the T120.
The SoCs are preconfigured with a RISC-V core, memory, a range of I/O, and have interfaces for embedding user functions. In this way, designers can create entire systems that include embedded compute and user defined accelerators within the same FPGA.
Efinix RISC-V SoCs come with a complete set of tools for compiling and debugging application code on the RISC-V core along with example applications and tutorials. They are compatible with the entire suite of Efinix development and evaluation boards and can be instantiated using the standard Efinity tool flow.
For more information, visit http://www.efinixinc.com.
Tiera Oliver is the assistant managing editor at Embedded Computing Design. She is responsible for web content editing, product news, and story development. She also manages, edits, and develops content for ECD podcasts, including Embedded Insiders.
She utilizes her expertise in journalism and content management to oversee editorial content, coordinate with editors, and ensure high-quality output across web, print, and multimedia platforms. She manages diverse projects, assists in the production of digital magazines, and hosts company podcasts by conducting in-depth interviews with industry leaders to deliver engaging and insightful discussions.
Tiera attended Northern Arizona University, where she received her bachelor's in journalism and political science. She was also a news reporter for the student-led newspaper, The Lumberjack.
