Open Source Paves the Way to More Flexible, More Responsive Processor Designs

By Davide Schiavone

Director of Engineering

Open Hardware Group

July 14, 2020


As the demand for increased functionality through advanced techniques such as data analytics and machine learning increases, the ability to handle software efficiently is vital to success.

The microprocessor plays a fundamental role in electronic design. As the demand for increased functionality through advanced techniques such as data analytics and machine learning increases, the ability to handle software efficiently is vital to success. To make the most of limited energy and silicon resources to this end we are seeing a demand in much greater use of tuned instruction sets and accelerators. Yet this is one area where manufacturers of end equipment have comparatively little control over the supply chain and what goes into these architectures.

Historically, processor-architecture development has been an expensive exercise and one that demands many years of R&D to make it successful. It’s no surprise that the choice of processor tends to be limited to a small number of dominant market players. If your needs do not align with theirs, you have to make do with what they make available.

Open source hardware provides the potential to realign the industry to be much more favorable to end-equipment manufacturers and designers of specialist silicon. A growing number of manufacturers are turning to the RISC-V architecture as the basis for their future plans because of the freedom it can give them without sacrificing the benefits many get from traditional architectures.

RISC-V itself is not a processor architecture. It is an open-source instruction set that has been honed over many years, taking advantage of the huge amount of experience that the embedded-systems and computing industries have accumulated in what makes some approaches work and others fail. Any silicon designer can take the RISC-V specification and use it to build their own custom processor without having to take out architectural licenses for existing proprietary offerings. However, although the licensing is far easier, architectural development remains an expensive and ambitious undertaking.

Because the RISC-V license itself is far more permissive than those provided by proprietary core vendors, a healthy ecosystem of open-source cores is springing up around it. Open-source cores themselves are not new. The European Space Agency, for example, was active in designing an open-source Sparc implementation with the Leon core. However, one traditional issue with open-source cores is that they had limited support and backing. The groundswell of support building for RISC-V is changing the picture, helped by the efforts of organizations such as the OpenHW Group. With members that span industry and academia, the group provides a forum for collaboration that seeks to accelerate the use and adoption of open-source SoC hardware based on RISC-V that will let manufacturers tune silicon to their specific needs.

In a webinar that will air live on Thursday, July 16, members of the OpenHW Group talk about a variety of projects that will help bring tunable cores to a diverse range of markets, from low-energy IoT, to high-performance computing. Designers within the group are using state-of-the-art tools to maximize scalability. A key example is a parameterizable version of the Ariane, where simple HDL directives make it possible to generate 32bit or 64bit implementations automatically. As engineers from the OpenHW Group describe in the webinar, users can easily make requests and initiate bugfixes through the organization’s Github repository. The end result will be a series of verified, silicon proven processors – written in a standard hardware description language such as System Verilog - that support the need for advanced edge processing far more efficiently than the supply chain that exists for proprietary cores. To sign up for the webinar, go to:

Davide Schiavone is a Ph.D. student at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group. He obtained BSc. and MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016, respectively. His main research focus is on low-power energy-efficient computer architectures for smart systems and human-machine interfaces. He visited the Centre of Bio-Inspired Technology at Imperial College London in the Next Generation Neural Interfaces group from Jan-June 2018.

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