Success Story: How RISC-V Is Enabling the Internet of Space

By Chad Cox

Associate Editor

Embedded Computing Design

December 14, 2022

Story

Image Provided by Amanda Janes

As objects exit Earth’s atmosphere, radiation levels become increasingly destructive to both organic and inorganic materials. The latter includes electronics, which are susceptible to Gamma rays, X-rays, and other high-energy particles that can cause single event upsets (SEUs, also known as bitflips) in memory, voltage spikes in analog circuitry, and other faults that can crash programs or entire systems.

Space radiation and its effects have been studied extensively over the past several decades. These efforts have resulted in the design and manufacture of radiation-hardened (rad-hard) electronics that use special materials, exotic shielding techniques, and undergo exhaustive testing to withstand ionizing forces beyond Earth’s atmosphere for deployable periods of time.

Today, the TRISAT-R nanosatellite – a collaboration between the European Space Agency (ESA), Cobham Advanced Electronic Solutions (CAES), Skylabs, and the University of Maribor in Slovenia – continues that tradition (Figure 1). And it’s doing so on the strength of open-source RISC-V processor technology.

Figure 1. The TRISAT-R is a research nanosatellite measuring the effects of ionizing radiation on commercial electronics in mid-earth orbit. (Source: SkyLabs)

 

RISC-V is Out of this World

The TRISAT-R CubeSat is a scientific and educational mission led by the University of Maribor to map ionizing radiation in medium Earth orbit (MEO), a 6000 km-high band around Earth where various positioning, defunct radio, and future communications satellites reside. Roughly the size of a shoebox, the 3U, 10 cm x 10 cm x 30 cm satellite is built around the NANOhpm-obc onboard computer from Slovenian space technology company SkyLabs (Figure 2).

Figure 2. SkyLabs NANOhpm-obc is the TRISAT-R’s onboard computer that equips a 32-bit Gaisler RISC-V processor for GNSS scintillation analysis and other tasks. (Source: SkyLabs)

Designed into a 95 mm x 91 mm x 11 mm PC/104-compliant form factor, the NANOhpm-obc is built around Cobham Gaisler’s fault-tolerant 32-bit NOEL-V RISC-V processor IP core implemented alongside a single-precision floating-point unit in a Microchip PolarFire FPGA. The onboard computer integrates 2 GB of ECC-protected DDR3 memory and 2 GB of NVM flash in an EDAC-protected 1 GB redundant configuration for telemetry data, logs, and the like.

On top of that hardware, SkyLabs layered its NANOsky CMM Firmware framework that provides the foundation for mission-specific applications and software functions.

To the knowledge of those involved in the project, when the NOEL-V processor onboard the NANOhpm-obc was launched into orbit on the ESA’s Vega-C rocket this summer, it marked the first time fault-tolerant RISC-V processor technology has been deployed in space.

The TRISAT-R is also outfitted with radiation detection instruments from SkyLabs, CERN, the European Council for Nuclear Research, and the European Space Agency (ESA) that measure the total ionization dose from high-energy particles as well as the effects of single ionizing events on electronics. These particles are analyzed locally on the nanosat using AI models, then radiation mitigation techniques are applied that show promise in extending the life of space bound COTS electronics. Communication between the nanosatellite’s various subsystems occurs over a redundant differential CAN bus for telemetry and telecommand (TMTC) data and LVDS for high-speed transfers.

The NANOhpm-obc’s 100 MIPS is leveraged for scintillation analysis of signals from an open GNSS receiver and to manage a software-defined radio (SDR) and 1.5 W VHF/UHF transmitter that relay radiation effect data to ground control stations.

Radiation Hardening is RISC-y Business

“We are striking quite a lot of energetic particles and the solution here was to design solar panels that are able to operate at that radiation,” says Iztok Kramberger, PhD, leader of the TRISAT project and member of the Electrical Engineering and Computer Science (FERI) faculty at the University of Maribor. “We increased the thickness of the cover glass for the solar panels by adding a serum to the cover glass and we added specific conductive transparent material to guard against electrostatic discharges.”

The irony here is that while the TRISAT-R is measuring radiation, it’s also being destroyed by it. In MEO, the Earth’s magnetic field is 6x weaker than in low Earth orbits (LEO) just a few thousand km below. It’s also a frigid -19-26 ºC. And since there are no service calls to replace defective CubeSat components in space, the TRISAT-R’s onboard electronics must survive long enough on their own to make the program worthwhile.

The aerospace industry has historically met such requirements with rad-hard electronics proven to work every single time over many years. This has led to significant technology reuse – understandable given that a single chip like the PowerPC-based RAD750 from BAE Systems controlling the Perseverance Rover costs hundreds of thousands of dollars per unit.

But as use cases evolve, so do platform requirements, and the need for higher fidelity sensors, more sensitive instrumentation, and increasingly sophisticated algorithms has surpassed the abilities of 32-bit, 200 MHz processors like the RAD750. But just as important, if not more so for the reliability-centric aerospace industry, software support for RISC architectures with long spaceflight heritages like PowerPC and SPARC is quickly evaporating.

“We have been using SPARC very successfully for more than 20 years. LEON 1 and 2 processor development was started at the European Space Agency,” says Roland Weigand, a VLSI and ASIC engineer at the ESA. “Now SPARC is of course a very old, almost obsolete standard. We’re still using products based on SPARC, but we are aware that, long-term, the software support, the maintenance, the improvement of compilers will stop or has already stopped.

“It’s been a couple years since the last commercial users, Fujitsu and Oracle, stopped supporting SPARC,” he adds.

These aren’t the only indicators that legacy technologies have run their course. For instance, features like delay slots built into SPARC processors that offset branch latency and allow one instruction to complete before a second enters the pipeline are now more of a programming nuisance than benefit. Similarly, register windows that facilitate “deep calling stacks in software is an obsolete feature,” Weigand explains.

Comparatively, Sandi Habinc, General Manager of Gaisler, believes that RISC-V offers “a simpler architecture” with “much more computing power per cycle.” The architectural optimizations of RISC-V mean that processors like the NOEL-V soft core can run at higher frequencies, which is critical in harsh environments like space because even if you use an advanced process node like 7 nm, so much radiation hardening is required around the processor core that it ends up being “10x slower than anything in the commercial world.”

“For us, every MHz we can bring to the table is important,” Habinc explains. “So definitely the simplicity of it is a huge advantage. The other one is of course implicitly built-in 16-bit support and the fact that we can now do microcontrollers and still use the same tools."

“What did we do on the controllers with LEON? We had to invent our own compressions, reduce instruction set, which is not really a smart way to do it. It’s great if you’re Arm and you have 10,000 engineers, but for us that was a painful exercise to go through that,” Habinc continues. “On SPARC, we never went beyond 32 bits because that would change the whole software environment and too much effort because we need to maintain quite a lot of software.

“With RISC-V, we can even scale down the cores we have today, reduce the number of pipeline stages, and really do a very thin single-stage, dual-stage microcontroller that we can fit everywhere,” the Gaisler GM goes on (Figure 3). “With RISC-V we can do the 32-bit microcontroller, we did a 64-bit version. Why not? It gives us the choice to target different uses in space.”

 

Figure 3. Gaisler has developed multiple iterations of the NOEL-V RISC-V processor IP, in 32- or 64-bit flavors with dual- or single-issue pipelines that support various RISC-V instruction set extensions. (Source: CAES)

To ease the transition for aerospace engineering organizations, Habinc and his team are working on a multicore processor that integrates both SPARC and RISC-V cores.

“We qualify one chip but there’s basically a pin saying you want to boot SPARC or RISC-V, and this gives a tremendous advantage,” he adds.

The Internet of Space

Gaisler has already developed different variants of the NOEL-V processor, some of which include extensions like vector processing that will further accelerate workloads in space. For researchers like Kramberger, the increase in processing power onboard spacecraft reduces management overhead and creates new opportunities for studying the final frontier.

“One advantage is that the spacecraft can be more autonomous, which means that you don’t have to manage 600 or 700 satellites. You can’t have people do that. It has to be more or less autonomous,” he explains. “The second thing is that we are improving the data transfer between the satellite and the ground because you’re able to do more processing at the edge.

“Then of course you can reduce the data downstream towards the Earth,” he continues. “So, for example, a typical remote sensing application still today, there is a camera recording, and this data is transferred to the Earth and on Earth we do things with the data. The resolution requires higher and higher data downlink bandwidth. But doing AI at the edge provides capabilities to take the interesting data within the orbit and transfer only the results, meaning much lower requirements on bandwidth.

“That is quite similar to the Internet of Things on Earth,” Kramberger progresses. “We could call it the ‘Internet of Space Assets’ that gives us the ability to do more sensing of our environment, which is not only the planet but the Solar System as such.”

For now, the TRISAT-R nanosatellite is fully operational in an elliptical orbit, “drifting between 18 and 23 degrees,” says Dejan Gačnik, CTO of SkyLabs. “All essential equipment has been commissioned … all parameters are nominal.”

Unfortunately for the TRISAT-R, the end is already near. Space radiation will eventually take its toll on the tiny satellite at which point it will have to be decommissioned. But given that its primary mission is to measure and analyze the effects of ionizing radiation on spacecraft electronics, Gačnik believes the mission will be a success if TRISAT-R can endure for at least six months. It has already been in orbit for almost four.

But for RISC-V, the TRISAT-R is just the beginning. Gaisler and the ESA continue to develop new generations of space processors based on the technology. Microchip, who has RISC-V technology deployed on the International Space Station, continues to advance it’s PolarFire FPGA portfolio with radiation-tolerant versions that include a SiFive soft CPU core for running user applications.

For organizations like ESA and NASA, RISC-V is the obvious choice as they continue to build space exploration programs on open, high-performance, and flexible commercial electronics.

“Going from one open standard to another open standard like RISC-V is the most logical choice,” Weigand says. “It’s simply an advance of technology, which helps improve the performance and the software development flow."

“For us, it’s a logical step forward.”

[Editor’s note: “RISC-V in Space” workshops are being held at the 2022 RISC-V Summit in San Jose, CA from December 12-15, and the European Space Agency’s GR740 user day at Erasmus Auditorium at ESTEC. Interested parties can access sessions virtually from the links below: