How and Why Chiplets are Growing in Use and Need

May 06, 2024

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Ever since Gordon Moore made his eponymous prediction in 1965, it’s been inevitable that we would reach an end to the ability to keep doubling the processing in individual chips, if only because of the laws of physics (at the macro scale anyway – we’ll cover quantum computing another time!).

Since Moore has been so reliably correct, well beyond even the time when many early doomsayers said we’d hit the limits, mostly thanks to advancements in materials science and electrical engineering, there haven’t been many solutions presented to the problem of reaching that Moore horizon. In fact, many times when the topic comes up it’s not unusual to see shrugging shoulders and waved hands as the majority responses. If ain’t broke (yet), why fix it?

Well, the insatiable hunger for ever more processing isn’t slowing down. In fact, if NVIDIA and their peers are to be believed, the desire and need is only accelerating. That’s why it’s critical to be developing creative solutions right now, and don’t worry the work is going on.

It’s certainly possible that the “spooky action at a distance” predicted and recently demonstrated by the quantum computing sciences will solve this problem (and I know I said that’s not what I’m doing in this piece), but that’s out in the unpredictable future and the world can’t wait.

We need a transitional technology that is both able to stretch computing until (if) quantum computing becomes commercially viable, and to offer capabilities that will be functional in all the multitude of use cases that won’t want or need such quantum options, should they become available.

Enter chiplets.

Chiplets have been around for a few years now, since AMD, Intel, ARM, and a few others each set out to solve this problem, in their own ways. Most basically, chiplets are processors that split functions like logic, memory & storage, and communications, I/O, analog into separate “chiplets” that get combined into one monolithic package joined by a low-latency connectivity matrix in a process called advanced packaging.

The advantage is that each segment can be improved from generation to generation, as technology and processes advance, even if other segments have not. That process allows some parts to be produced with newer, more powerful methods and others to be made according to established processes that might be more economical or efficient. In this way, the total “chip” can advance while the process stays efficient and stable, even if parts of it are slowing against Moore’s Law.

There are several indicators that this is working.

The MIT Technology Review reported that Chinese companies and government-run development agencies are investigating and investing in chiplets as a way around both Moore’s law and US sanctions on semiconductors. Chinese companies are already responsible for nearly 40 percent of chip packaging in the world as of November last year, according to Bloomberg.

China’s top state research fund last year committed between $4 and $6.5 million in funding to chiplet projects over the next four years, and in Wuxi a city in eastern China, government officials have reportedly proposed establishing a $14 million fund for chiplet business development.

That’s just one example of a global power getting on board with chiplets in a big way. Of course, in the US, AMD and Intel have led the way with chiplet development and with new semiconductor facilities opening all over the states, thanks in part to last year’s infrastructure bill, that growth won’t be slowing any time soon.

In Japan, the forces driving chiplet investment are also moving rapidly. Tenstorrent announced in February that it has licensed three chiplet designs to Japan’s Leading-edge Semiconductor Technology Center (LSTC).

Tenstorrent said it will work closely with a new Japanese Semiconductor company called Rapidus Corporation to develop logic semiconductor tech. The Tenstorrent Ascalon RISC-V CPU core reportedly will be used to co-develop a RISC-V CPU chiplet for the LSTC’s new edge AI accelerator.

The chiplet technology is also improving as these investments roll out, and the standards are being defined.

Keysight has seen that movement and recently introduced a Chiplet PHY Designer for Simulating die-to-die (D2D) interconnect PHY IP that supports the Universal Chiplet Interconnect Express (UCIe) standard, according to a recent release.  

The D2D sim is important to verifying performance in chiplets, and this electronic design automation (EDA) tool is designed to provide in-depth modeling and simulation capabilities for chiplet designers to use in verifying that designs meet the UCIe standard. 

UCIe is an open chiplet specification standard that defines the interconnect between chiplets within an advanced 2.5D or 3D package. Many of the top semiconductor equipment and EDA tool vendors are supporting or exploring UCIe, in addition to foundries and chiplet designers.

ARM is also advocating for standards discussions for chiplets. This year, the company outlined its plan for the Arm Chiplet System Architecture (CSA), which the company said it’s been working on with more than 20 partners. They’ve reportedly been analyzing and defining optimal partitioning choices for chiplet-based systems to develop the CSA. The goal, the company said, is to standardize system design choices for different chiplet types, for example, how to partition an Arm-based system across multiple chiplets, or their requirements for system memory or a Root of Trust.

There are many signs and developments that indicate the need and growth of chiplet designs and implementations. I know I won’t be surprised as it happens.